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ADIN1101BCPZ-R7 数据表(PDF) 63 Page - Analog Devices |
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ADIN1101BCPZ-R7 数据表(HTML) 63 Page - Analog Devices |
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63 / 79 page  Data Sheet ADIN1101 REGISTER SUMMARY analog.com Rev. A | 63 of 79 Vendor Specific Device 1 and Vendor Specific Device 2 MMDs are present. Table 95. Bit Descriptions for MMD1_DEVS_IN_PKG2 Bits Bit Name Description Reset Access [15:0] MMD1_DEVS_IN_PKG2 Vendor Specific 1 MMD Devices in Package 2. Vendor Specific Device 1 and Vendor Specific Device 2 MMDs are present. 0xC000 R Vendor Specific MMD 1 Status Register Device Address: 0x1E; Register Address: 0x0008, Reset: 0x8000, Name: MMD1_STATUS This address corresponds to the Vendor Specific MMD 1 status register specified in Subclause 45.2.11.2 of Standard 802.3. Table 96. Bit Descriptions for MMD1_STATUS Bits Bit Name Description Reset Access [15:14] MMD1_STATUS Vendor Specific 1 MMD Status. 0x2 R 10: device responding at this address. 11: no device responding at this address. 01: no device responding at this address. 00: no device responding at this address. [13:0] RESERVED Reserved. 0x0 R System Interrupt Status Register Device Address: 0x1E; Register Address: 0x0010, Reset: 0x1000, Name: CRSM_IRQ_STATUS This address can be used to check which interrupt requests have been triggered since the last time it was read. Each bit goes high when the associated event occurs and then latches high until it is unlatched by reading. The bits of CRSM_IRQ_STATUS go high even when the associated interrupts are not enabled. A reserved interrupt being triggered indicates a fatal error in the system. Table 97. Bit Descriptions for CRSM_IRQ_STATUS Bits Bit Name Description Reset Access 15 CRSM_SW_IRQ_LH Software Requested Interrupt Event. 0x0 R LH [14:13] RESERVED Reserved. 0x0 R 12 CRSM_HRD_RST_IRQ_LH Hardware Reset Interrupt. 0x1 R LH [11:0] RESERVED Reserved. 0x0 R LH System Interrupt Mask Register Device Address: 0x1E; Register Address: 0x0020, Reset: 0x1BFE, Name: CRSM_IRQ_MASK Controls whether or not the interrupt signal is asserted in response to various events. Table 98. Bit Descriptions for CRSM_IRQ_MASK Bits Bit Name Description Reset Access 15 CRSM_SW_IRQ_REQ Software Interrupt Request. Software can set this bit to generate an interrupt for system level testing. This bit always reads as 0 because it is self clearing. 0x0 R/W SC [14:13] RESERVED Reserved. 0x0 R 12 CRSM_HRD_RST_IRQ_EN Enable Hardware Reset Interrupt. Note that writing a 0 to this register does not mask the interrupt since this register is initialized when a hardware reset occurs. 0x1 R/W [11:0] RESERVED Reserved. 0xBFE R/W |
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