ADIN1101BCPZ-R7 datasheet(75/79 Pages) AD

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Data Sheet

ADIN1101

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Rev. A | 75 of 79

Frame Generator Continuous Mode Enable Register

Device Address: 0x1F; Register Address: 0x8022, Reset: 0x0000, Name: FG_CONT_MODE_EN

This register is used to put the frame generator into continuous mode. The default mode of operation is burst mode, where the number of

frames generated is specified by the FG_NFRM_H and FG_NFRM_L registers.

Table 137. Bit Descriptions for FG_CONT_MODE_EN

Bits

Bit Name

Description

Reset

Access

[15:1]

RESERVED

Reserved.

0x0

FG_CONT_MODE_EN

Frame Generator Continuous Mode Enable. This bit is used to put the frame generator into

continuous mode or burst mode.

0x0

R/W

1: frame generator operates in continuous mode. In this mode, the frame generator keeps

generating frames indefinitely.

0: frame generator operates in burst mode. In this mode, the frame generator generates a single

burst of frames and then stops. The number of frames is determined by the FG_NFRM_H and

FG_NFRM_L registers.

Frame Generator Interrupt Enable Register

Device Address: 0x1F; Register Address: 0x8023, Reset: 0x0000, Name: FG_IRQ_EN

This register is used to enable the frame generator interrupt. An interrupt is generated when the requested number of frames has been

generated. Enable the frame checker/generator interrupt in the PHY_SUBSYS_IRQ_MASK register. Set the MAC_IF_FC_FG_IRQ_EN bit.

The interrupt status can be read via the MAC_IF_FC_FG_IRQ_LH bit in the PHY_SUBSYS_IRQ_STATUS register.

Table 138. Bit Descriptions for FG_IRQ_EN

Bits

Bit Name

Description

Reset

Access

[15:1]

RESERVED

Reserved.

0x0

FG_IRQ_EN

Frame Generator Interrupt Enable. When set, this bit indicates that the frame generator must generate an

interrupt when it has transmitted the programmed number of frames.

0x0

R/W

1: enable the frame generator interrupt.

0: disable the frame generator interrupt.

Frame Generator Frame Length Register

Device Address: 0x1F; Register Address: 0x8025, Reset: 0x006B, Name: FG_FRM_LEN

This register specifies the data field frame length in bytes. In addition to the data field, six bytes are added for the source address, six bytes

for the destination address, two bytes for the length field, and four bytes for the frame check sequence (FCS). The total length is the data field

length plus 18.

Table 139. Bit Descriptions for FG_FRM_LEN

Bits

Bit Name

Description

Reset

Access

[15:0]

FG_FRM_LEN

The Data Field Frame Length in Bytes.

0x6B

R/W

Frame Generator Interframe Gap Length Register

Device Address: 0x1F; Register Address: 0x8026, Reset: 0x000C, Name: FG_IFG_LEN

This register specifies the length in bytes of the interframe gap to be inserted between frames by the frame generator.

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