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ADIN1101BCPZ-R7 数据表(PDF) 74 Page - Analog Devices |
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ADIN1101BCPZ-R7 数据表(HTML) 74 Page - Analog Devices |
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74 / 79 page  Data Sheet ADIN1101 REGISTER SUMMARY analog.com Rev. A | 74 of 79 Frame Checker Odd Preamble Packet Count Register Device Address: 0x1F; Register Address: 0x8011, Reset: 0x0000, Name: FC_ODD_PRE_CNT This register is a latched copy of the odd preamble packet counter register. This register is a count of received packets with an odd number of nibbles in the preamble. When the receive error counter (RX_ERR_CNT) is read, the odd preamble packet counter register is latched, which ensures that the odd preamble packet count and the receive frame count are synchronized. Table 133. Bit Descriptions for FC_ODD_PRE_CNT Bits Bit Name Description Reset Access [15:0] FC_ODD_PRE_CNT Latched Copy of the Odd Preamble Packet Counter. 0x0 R Frame Checker False Carrier Count Register Device Address: 0x1F; Register Address: 0x8013, Reset: 0x0000, Name: FC_FALSE_CARRIER_CNT This register is a latched copy of the false carrier events counter register. This is a count of the number of times the bad SSD state is entered. When the receive error counter (RX_CNT_ERR) is read, the false carrier events counter register is latched, which ensures that the false carrier events count and the receive frame count are synchronized. Table 134. Bit Descriptions for FC_FALSE_CARRIER_CNT Bits Bit Name Description Reset Access [15:0] FC_FALSE_CARRIER_CNT Latched Copy of the False Carrier Events Counter. 0x0 R Frame Generator Enable Register Device Address: 0x1F; Register Address: 0x8020, Reset: 0x0000, Name: FG_EN This register is used to enable the frame generator. When the frame generator is enabled, the source of data for the PHY comes from the frame generator and not the MAC interface. To use the frame generator, the diagnostic clock must also be enabled (DIAG_CLK_EN). Table 135. Bit Descriptions for FG_EN Bits Bit Name Description Reset Access [15:1] RESERVED Reserved. 0x0 R 0 FG_EN Frame Generator Enable. 0x0 R/W Frame Generator Control/Restart Register Device Address: 0x1F; Register Address: 0x8021, Reset: 0x0001, Name: FG_CNTRL_RSTRT This register controls the frame generator. The FG_CNTRL bit field specifies data field type used by the frame generator, for example, random or all zeros. The FG_RSTRT bit restarts the frame generator. Table 136. Bit Descriptions for FG_CNTRL_RSTRT Bits Bit Name Description Reset Access [15:4] RESERVED Reserved. 0x0 R 3 FG_RSTRT Frame Generator Restart. When set, this bit restarts the frame generator. This bit is self clearing. 0x0 R/W SC [2:0] FG_CNTRL Frame Generator Control. 0x1 R/W 000: no frames after completion of current frame. 001: random number data frame. 010: all zeros data frame. 011: all ones data frame. 100: alternative 0x55 data field. 101: data field decrementing from 255 (decimal) to 0. |
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