ST7LITE0XY0 datasheet(73/124 Pages) STMICROELECTRONICS

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ST7LITE0xY0, ST7LITESxY0

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8-BIT A/D CONVERTER (ADC) (Cont’d)

11.4.6 Register Description

CONTROL/STATUS REGISTER (ADCCSR)

Read/Write

Reset Value: 0000 0000 (00h)

Bit 7 = EOC Conversion Complete

This bit is set by hardware. It is cleared by soft-

ware reading the result in the DR register or writing

to the CSR register.

0: Conversion is not complete

1: Conversion can be read from the DR register

Bit 6 = SPEED ADC clock selection

This bit is set and cleared by software. It is used

together with the SLOW bit to configure the ADC

clock speed. Refer to the table in the SLOW bit de-

scription.

Bit 5 = ADON A/D Converter and Amplifier On

This bit is set and cleared by software.

0: A/D converter and amplifier are switched off

1: A/D converter and amplifier are switched on

Note: Amplifier not available on ST7LITES5

devices

Bits 4:3 = Reserved. must always be cleared.

Bits 2:0 = CH[2:0] Channel Selection

These bits are set and cleared by software. They

select the analog input to convert.

Notes:

1. The number of pins AND the channel selection

varies according to the device. Refer to the device

pinout.

2. A write to the ADCCSR register (with ADON set)

aborts the current conversion, resets the EOC bit

and starts a new conversion.

DATA REGISTER (ADCDR)

Read Only

Reset Value: 0000 0000 (00h)

Bits 7:0 = D[7:0] Analog Converted Value

This register contains the converted analog value

in the range 00h to FFh.

Note: Reading this register reset the EOC flag.

AMPLIFIER CONTROL REGISTER (ADCAMP)

Read/Write

Reset Value: 0000 0000 (00h)

Bit 7:4 = Reserved. Forced by hardware to 0.

Bit 3 = SLOW Slow mode

This bit is set and cleared by software. It is used

together with the SPEED bit to configure the ADC

clock speed as shown on the table below.

Bit 2 = AMPSEL Amplifier Selection Bit

This bit is set and cleared by software. For

ST7LITES5 devices, this bit must be kept at its re-

set value (0).

0: Amplifier is not selected

1: Amplifier is selected

Note: When AMPSEL=1 it is mandatory that fADC

be less than or equal to 2 MHz.

Bits 1:0 = Reserved. Forced by hardware to 0.

Note: If ADC settings are changed by writing the

ADCAMP register while the ADC is running, a

dummy conversion is needed before obtaining re-

sults with the new settings.

EOC

SPEED ADON

CH2

CH1

CH0

Channel Pin1

CH2

CH1

CH0

AIN0

AIN1

AIN2

AIN3

AIN4

000

SLOW

AMP-

SEL

fADC

SLOW SPEED

fCPU/2

fCPU

fCPU/4

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