ST7LITE0XY0 datasheet(86/124 Pages) STMICROELECTRONICS

86 / 124 page

ST7LITE0xY0, ST7LITESxY0

86/124

OPERATING CONDITIONS (Cont’d)

13.3.4.2 Devices with ‘”6” order code suffix (tested for TA = -40 to +85°C) @ VDD = 2.7 to 3.3V

Notes:

1. If the RC oscillator clock is selected, to improve clock stability and frequency accuracy, it is recommended to place a

decoupling capacitor, typically 100nF, between the VDD and VSS pins as close as possible to the ST7 device.

2. See “INTERNAL RC OSCILLATOR ADJUSTMENT” on page 24.

3. Data based on characterization results, not tested in production

4. Averaged over a 4ms period. After the LOCKED bit is set, a period of tSTAB is required to reach ACCPLL accuracy

5. After the LOCKED bit is set ACCPLL is max. 10% until tSTAB has elapsed. See Figure 13 on page 25.

6. Guaranteed by design.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

fRC

Internal RC oscillator fre-

quency

RCCR = FF (reset value), TA=25°C, VDD= 3.0V

560

kHz

RCCR=RCCR12) ,TA=25°C, VDD= 3V

700

ACCRC

Accuracy of Internal RC

oscillator when calibrated

with RCCR=RCCR12)3)

TA=25°C,VDD=3V

-2

TA=25°C,VDD=2.7 to 3.3V

-25

+25

TA=-40 to +85°C, VDD=3V

-15

IDD(RC)

RC oscillator current con-

sumption

TA=25°C,VDD=3V

7003)

µA

tsu(RC)

RC oscillator setup time

TA=25°C,VDD=3V

102)

µs

fPLL

x4 PLL input clock

0.73)

MHz

tLOCK

PLL Lock time5)

2ms

tSTAB

PLL Stabilization time5)

4ms

ACCPLL

x4 PLL Accuracy

fRC = 1MHz@TA=25°C, VDD=2.7 to 3.3V

0.14)

fRC = 1MHz@TA=40 to +85°C, VDD= 3V

0.14)

tw(JIT)

PLL jitter period

fRC = 1MHz

86)

kHz

JITPLL

PLL jitter (

∆f

CPU/fCPU)1

IDD(PLL)

PLL current consumption TA=25°C

1903)

µA

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