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ST7LITE0XY0 数据表(PDF) 35 Page - STMicroelectronics |
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ST7LITE0XY0 数据表(HTML) 35 Page - STMicroelectronics |
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35 / 124 page ![]() ST7LITE0xY0, ST7LITESxY0 35/124 SYSTEM INTEGRITY MANAGEMENT (Cont’d) 8.4.3 Low Power Modes 8.4.3.1 Interrupts The AVD interrupt event generates an interrupt if the corresponding Enable Control Bit (AVDIE) is set and the interrupt mask in the CC register is re- set (RIM instruction). Mode Description WAIT No effect on SI. AVD interrupts cause the device to exit from Wait mode. HALT The SICSR register is frozen. The AVD remains active but the AVD inter- rupt cannot be used to exit from Halt mode. Interrupt Event Event Flag Enable Control Bit Exit from Wait Exit from Halt AVD event AVDF AVDIE Yes No 1 |
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