Data Sheet

ADL6332

SPECIFICATIONS

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Rev. A | 7 of 55

Table 2. Specifications (Continued)

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

V33AMP1

3.135

3.3

3.465

V

V33AMP2A

3.135

3.3

3.465

V

V33AMP2

3.135

3.3

3.465

V

V33FUSE

3.135

3.3

3.465

V

Current

Full Fixed Gain Mode1

3.3 V supply

V33AMP1A

80

mA

V33AMP1

160

mA

V33AMP2A

80

mA

V33AMP2

160

mA

V33FUSE

35

mA

AMP1 Bypass Attenuation Mode2

3.3 V supply

V33AMP1A

2

mA

V33AMP1

0.1

mA

V33AMP2A

80

mA

V33AMP2

160

mA

V33FUSE

22

mA

AMP2 Bypass Attenuation Mode2

3.3 V supply

V33AMP1A

80

mA

V33AMP1

160

mA

V33AMP2A

0.1

mA

V33AMP2

0.1

mA

V33FUSE

22

mA

AMP1 and AMP2 Bypass Attenuation Mode2

3.3 V supply

V33AMP1A

2

mA

V33AMP1

0.1

mA

V33AMP2A

0.1

mA

V33AMP2

0.1

mA

V33FUSE

12

mA

Power-Down Mode

3.3 V supply

3

mA

1 The full fixed gain mode is configured with the fixed gain configurations in AMP1 and AMP2, and DSA = 0 dB with the factory optimized parameters.

2 The bypass attenuation mode is configured with the bypass settings in AMP1 or AMP2, and DSA = 0 dB with the factory optimized parameters. Bypassing an amplifier with

the attenuation mode reduces the total current typically by 230 mA per amplifier.

3 OIP2L refers to the two tone difference frequency, OIP2H refers to the two tone summation frequency.

4 IIP2L refers to the two tone difference frequency, IIP2H refers to the two tone summation frequency.

5 Exceeds the absolute maximum rating.

6 Not applicable. For ADL6332-A, an input signal frequency ≥ 4 GHz makes OIP2H/IIP2H beyond the operating frequency range.

7 Not applicable. For ADL6332-B, an input signal frequency ≥ 7.5 GHz makes OIP2H/IIP2H beyond the operating frequency range.

DIGITAL LOGIC TIMING

CLOAD = 25 pF

Table 3. SPI Timing Specifications

Parameter

Description

Min

Typ

Max

Unit

fSCLK

Maximum serial-clock rate

25

MHz

tPWH

Minimum period that SCLK is in logic-high state

10

ns

tPWL

Minimum period that SCLK is in logic-low state

10

ns