Data Sheet

ADPL42005

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Rev. 0

16 of 26

Figure 41. Typical Adjustable Output Voltage Application Schematic

The value of R2 must be less than 200kΩ to minimize errors in the output voltage caused by the ADJ pin input current.

For example, when R1 and R2 each equal 200kΩ, the output voltage is 2.44V. The output voltage error introduced by

the ADJ pin input current is 2mV or 0.08%, assuming a typical ADJ pin input current of 10nA at 25°C.

The ADPL42005 uses the EN/UVLO pin to enable and disable the VOUT pin under normal operating conditions. When

EN/UVLO is high, VOUT turns on, and when EN is low, VOUT turns off. For automatic startup, EN/UVLO can be tied to VIN.

The ADPL42005 incorporates reverse current protections circuitry that prevents current flow backwards through the

pass element when the output voltage is greater than the input voltage. A comparator senses the difference between

the input and output voltages. When the difference between the input voltage and output voltage exceeds 55mV, the

body of the PFET is switched to VOUT and turned off or opened. In other words, the gate is connected to VOUT.

VOUT = 5V

VIN = 8V

PG

VOUT

VIN

PG

GND

ADJ

EN/

UVLO

RPG

100kΩ

R4

100kΩ

R3

100kΩ

COUT

1µF

CIN

1µF

ON

OFF

R2

13kΩ

+

+

R1

40.2kΩ

ADPL42005