Data Sheet

ADPL42005

analog.com

Rev. 0

20 of 26

Figure 47. Typical Power-Good Threshold vs. Temperature, VOUT Falling

Noise Reduction of the ADPL42005 in Adjustable Mode

The ultralow output noise of the fixed output ADPL42005 is achieved by keeping the LDO error amplifier in unity gain

and setting the reference voltage equal to the output voltage. This architecture does not work for an adjustable

output voltage LDO. The adjustable output ADPL42005 uses the more conventional architecture, where the reference

voltage is fixed and the error amplifier gain is a function of the output voltage. The disadvantage of the conventional

LDO architecture is that the output voltage noise is proportional to the output voltage.

The adjustable LDO circuit can be modified slightly to reduce the output voltage noise to levels close to that of the

fixed output ADPL42005. The circuit shown in Figure 48 adds two additional components to the output voltage

setting resistor divider. CNR and RNR are added in parallel with RFB1 to reduce the ac gain of the error amplifier. RNR is

chosen to be equal to RFB2. This limits the AC gain of the error amplifier to approximately 6dB. The actual gain is the

parallel combination of RNR and RFB1 divided by RFB2. This ensures the error amplifier always operates at greater than

unity gain.

CNR is chosen by setting the reactance of CNR equal to RFB1 − RNR at a frequency between 50Hz and 100Hz. This sets the

frequency where the AC gain of the error amplifier is 3dB down from its DC gain.

Figure 48. Noise Reduction Modification to Adjustable LDO

Current Limit and Thermal Overload Protection

The ADPL42005 is protected against damage due to excessive power dissipation by current and thermal overload

protection circuits. The ADPL42005 is designed to current limit when the output load reaches 775mA (typical). When

the output load exceeds 775mA, the output voltage is reduced to maintain a constant current limit.

Thermal overload protection is included, which limits the junction temperature to a maximum of 150°C (typical).

Under extreme conditions (that is, high ambient temperature and/or high power dissipation) when the junction

temperature starts to rise above 150°C, the output is turned off, reducing the output current to zero. When the

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4.2

4.3

4.4

4.5

4.6

4.7

4.8

4.9

5.0

VOUT (V)

PG –40°C

PG –5°C

PG +25°C

PG +85°C

PG +125°C

VOUT = 5V

VIN = 8V

PG

VOUT

VIN

PG

GND

ADJ

EN/

UVLO

COUT

1µF

CIN

1µF

ON

OFF

RNR

13kΩ

RFB2

13kΩ

+

+

RFB1

40.2kΩ

CNR

100nF

+

RPG

100kΩ

R2

100kΩ

R1

100kΩ

ADPL42005