Data Sheet

ADPL42005

analog.com

Rev. 0

18 of 26

Figure 43. Typical VOUT Response to EN Pin Operation

The upper and lower thresholds are user programmable and can be set using two resistors. When the EN/UVLO pin

voltage is below 1.22V, the LDO is disabled. When the EN/UVLO pin voltage transitions above 1.22V, the LDO is

enabled and 10µA hysteresis current is sourced out from the pin raising the voltage, thus providing threshold

hysteresis. Typically, two external resistors program the minimum operational voltage for the LDO. The resistance

values, R1 and R2, can be determined from:

R1 = VHYS/10μA

R2 = 1 . 22V × R1/(VIN − 1 . 22V)

where:

VIN is the desired turn-on voltage.

VHYS is the desired EN/UVLO hysteresis level.

Hysteresis can also be achieved by connecting a resistor in series with the EN/UVLO pin. For the example shown in

Figure 44, the enable threshold is 2.44V with a hysteresis of 1V.

Figure 44. Typical EN Pin Voltage Divider

Figure 43 shows the typical hysteresis of the EN/UVLO pin. This prevents on/off oscillations that can occur because

of noise on the EN pin as it passes through the threshold points.

The ADPL42005 uses an internal soft-start to limit the inrush current when the output is enabled. The startup time

for the 3.3V option is approximately 580μs from the time the EN active threshold is crossed to when the output

reaches 90% of its final value. As shown in Figure 45, the startup time is dependent on the output voltage setting.

1.25

1.50

1.75

2.00

2.25

2.50

2.75

3.00

1.00

VOUT, EN RISE

VOUT, EN FALL

VOUT = 5V

VIN = 8V

PG

VOUT

VIN

PG

GND

SENSE

EN/

UVLO

RPG

100kΩ

R2

100kΩ

R1

100kΩ

COUT

1µF

CIN

1µF

ON

OFF

+

+

ADPL42005