ADL6331ACCZA-R7 datasheet(36/54 Pages) AD

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Data Sheet

ADL6331

APPLICATIONS INFORMATION

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Rev. B | 36 of 54

CURRENT CONSUMPTION OPTIMIZATION

When the MSB in Register 0x104, Register 0x105, and Register

0x106 for AMP1 and Register 0x110, Register 0x111, and Register

0x112 for AMP2 are set to 0, these six registers are tunable by

the user. If lesser current consumption is needed, the settings

of both AMP1_IGREF in Register 0x104 and AMP2_IGREF in

of factory trimmed IGREF in Register 0x140 and Register 0x143

for AMP1 and AMP2, respectively. See Figure 96 and Figure 97.

As a result of reducing AMP1_IGREF and AMP2_IGREF, the OIP3

performance degrades as shown in Figure 98 and Figure 99.

It is not recommended to increase the IGREF settings greater than

the readback value for AMP1 and AMP2 and doing so could impact

the long term reliability of the part.

Figure 96. Total Current vs. IGREF Settings for Various Frequencies

(ADL6331-A)

Figure 97. Total Current vs. IGREF Settings for Various Frequencies

(ADL6331-B)

Figure 98. OIP3 vs. IGREF Settings for Various Frequencies (ADL6331-A)

Figure 99. OIP3 vs. IGREF Settings for Various Frequencies (ADL6331-B)

AC COUPLING

The ESD clamps are located immediately following the input ports

and prior to the output port (see Figure 100). When a DC voltage

greater than or equal to 1.0 V is applied as common mode, there

is a risk of latching the silicon controlled rectifier (SCR) clamps

in the ESD protection block with a single spike. Even with a DC

voltage less than 1 V, intermodulation performance of the part may

be degraded. An external DC block capacitor for AC coupling is

always recommended.

Figure 100. Simplified RF Input and Output Port Structure

ADL6331ACCZA-R7 数据表(PDF) 36 Page - Analog Devices