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ADL6331ACCZA-R7 数据表(PDF) 43 Page - Analog Devices |
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ADL6331ACCZA-R7 数据表(HTML) 43 Page - Analog Devices |
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43 / 54 page ![]() Data Sheet ADL6331 REGISTER DETAILS analog.com Rev. B | 43 of 54 Table 33. Bit Descriptions for SIG_PATH2_0 Bits Bit Name Description Reset Access [7:3] RESERVED Reserved. 0x0 R 2 SIGCHAIN_BYPASS Bypass Signal Chain Mode. 0x0 R/W 0: Based on Individual Amp Bypass Setting. 1: Bypass Both Amps. 1 SEL_IBIASGEN_BG Select Bias Generator PTAT BG Reference (Debug Only). 0x0 R/W 0: Use Dedicated PTAT Generator (Default). 1: Use Bandgap Based PTAT Generator. 0 RESERVED Reserved. 0x0 R/W Address: 0x103, Reset: 0x06, Name: SIG_PATH0_1 Table 34. Bit Descriptions for SIG_PATH0_1 Bits Bit Name Description Reset Access [7:4] RESERVED Reserved. 0x0 R 3 AMP1_MON_EN Amp 1 Enable Bias Monitors. 0x0 R/W 0: Disable Bias Monitoring. 1: Enable Bias Monitoring (Debug Only). 2 RESERVED Reserved. 0x1 R/W 1 AMP1_IM3_EN Amp 1 Enable IM3 Trim Currents. 0x1 R/W 0: Disable IM3 Trim Currents. 1: Enable IM3 Trim Currents. 0 AMP1_LP_MODE AMP1 Low Power Mode (Disables IM3 Trim). 0x0 R/W 0: Disable. Use Default Bias. 1: Enable Low Bias. Address: 0x104, Reset: 0x89, Name: SIG_PATH1_1 Table 35. Bit Descriptions for SIG_PATH1_1 Bits Bit Name Description Reset Access 7 NVM_TRM_AMP1_IGREF Select Fused Value of TRM_AMP1_IGREF. 0x1 R/W [6:4] RESERVED Reserved. 0x0 R [3:0] AMP1_IGREF Amp 1 Main Gain Bias Trim (LSB = 10mA). 0x9 R/W |
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