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ADL6331ACCZA-R7 数据表(PDF) 48 Page - Analog Devices

部件名 ADL6331ACCZA-R7
功能描述  0.38 GHz to 15 GHz TxVGA
PDF  54 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADL6331ACCZA-R7 数据表(HTML) 48 Page - Analog Devices

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Data Sheet
ADL6331
REGISTER DETAILS
analog.com
Rev. B | 48 of 54
Table 42. Bit Descriptions for SIG_PATH3_2 (Continued)
Bits
Bit Name
Description
Reset
Access
10001: 17dB.
10010: 18dB.
10011: 19dB.
10100: 20dB.
10101: 21dB.
10110: 22dB.
10111: 23dB.
11000: 24dB.
Address: 0x10F, Reset: 0x06, Name: SIG_PATH0_3
Table 43. Bit Descriptions for SIG_PATH0_3
Bits
Bit Name
Description
Reset
Access
[7:4]
RESERVED
Reserved.
0x0
R
3
AMP2_MON_EN
Amp 2 Enable Bias Monitors.
0x0
R/W
0: Disable Bias Monitoring.
1: Enable Bias Monitoring (Debug Only).
2
AMP2_CROSS_EN
Amp 1 Enable Cross IM3 Trim Currents.
0x1
R/W
0: Disable Cross-Coupled Stage IM3 Trim.
1: Enable Cross-Coupled Stage IM3 Trim.
1
AMP2_IM3_EN
Amp 2 Enable IM3 Trim Currents.
0x1
R/W
0: Disable IM3 Trim Currents.
1: Enable IM3 Trim Currents.
0
AMP2_LP_MODE
AMP2 Low Power Mode (Disables IM3 Trim).
0x0
R/W
0: Disable. Use Default Bias.
1: Enable Low Bias.
Address: 0x110, Reset: 0x89, Name: SIG_PATH1_3
Table 44. Bit Descriptions for SIG_PATH1_3
Bits
Bit Name
Description
Reset
Access
7
NVM_TRM_AMP2_IGREF
Select Fused Value of TRM_AMP2_IGREF.
0x1
R/W
[6:4]
RESERVED
Reserved.
0x0
R
[3:0]
AMP2_IGREF
Amp 2 Main Gain Bias Trim (LSB = 10mA).
0x9
R/W
Address: 0x111, Reset: 0xAA, Name: SIG_PATH2_3



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