Data Sheet

ADRF5010

THEORY OF OPERATION

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Rev. 0 | 10 of 12

The ADRF5010 can interface CMOS-/LVTTL-compatible control

interfaces directly.

CTRL determines which RF ports are in the insertion loss state and

in the isolation state. For the control voltage truth table, see Table 7.

RF INPUT AND OUTPUT

The RF ports (RF1 and RF2) are DC-coupled to 0 V and no DC

blocking is required at the RF ports when the RF line potential is

equal to 0 V.

The RF ports are internally matched to 50 Ω. However, impedance

matching on transmission lines can be used to improve insertion

loss and return loss performances at high frequencies.

The ADRF5010 is bidirectional with equal power handling capabili-

ties.

The insertion loss path conducts the RF signal between the RF1

and RF2 ports. The isolation path provides high loss between RF1

and RF2 ports which are 50 Ω terminated.

The power handling of the ADRF5010 derates with frequency below

0.1 GHz. For derating of the RF power toward lower frequencies,

see Figure 2.

The ADRF5010 requires a positive supply voltage applied to the

VDD pin and a negative supply voltage applied to the VSS pin.

Bypassing capacitors are recommended on the supply lines to

minimize RF coupling.

The ideal power-up sequence is as follows:

1. Connect GND.

2. Power up VDD and VSS. Power up VSS after VDD to avoid

current transients on VDD during ramp-up.

3. Power up the digital control inputs. The relative order of the log-

ic control inputs is not important. However, powering the digital

control inputs before the VDD supply can inadvertently forward

bias and damage the internal ESD protection structures.

4. Apply signals to the RF input ports.

Table 7. Control Voltage Truth Table

Digital Control Input

RFx Paths

CTRL

RF1 to RF2

Low

Insertion loss (on)

High

Isolation (off)