Data Sheet

ADRF5010

APPLICATIONS INFORMATION

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Rev. 0 | 11 of 12

EVALUATION BOARD

The ADRF5010 has two power supply pins (VDD and VSS) and

one control pin (CTRL). Figure 17 shows the external components

and connections for the supply pin. The VDD and VSS pins are

decoupled with a 100 pF multilayer ceramic capacitor. The device

pin-out allows the placement of the decoupling capacitors close to

the device. No other external components are needed for bias and

operation, except DC blocking capacitors on the RF pins when the

RF lines are biased at a voltage different than 0 V. For more details,

see the Pin Configuration and Function Description section.

Figure 17. Recommended Schematic

RECOMMENDATIONS FOR PRINTED CIRCUIT

BOARD DESIGN

The RF ports are matched to 50 Ω internally, and the pinout is

designed to mate a coplanar waveguide (CPWG) with 50 Ω charac-

teristic impedance on the PCB. Figure 18 shows the referenced

CPWG RF trace design for an RF substrate with 8 mil thick Rogers

RO4003C dielectric material. The RF trace with 14 mil width and 7

mil clearance is recommended for 1.5 mil finished copper thickness.

Figure 18. Example PCB Stack-Up

Figure 19 shows the routing of the RF traces, supply, and control

signals from the device. The ground planes are connected with

densely filled through vias for optimal RF and thermal performance.

The primary thermal path for the device is the bottom side.

Figure 19. PCB Routing

Figure 20 shows the recommended layout from the device RF pins

to the 50 Ω CPWG on the referenced stack-up. PCB pads are

drawn 1:1 to device pads. The ground pads are drawn soldermask

defined and the signal pads are drawn as pad defined. The RF

trace from the PCB pad is extended with the same width until

the package edge and tapered to RF trace. The paste mask is

designed to match the device pads without any aperture reduction.

The paste mask is divided into multiple openings for the paddle.

Figure 20. Recommended RF Pin Transition

For alternate PCB stack-ups with different dielectric thickness and

RF trace design, and for further recommendations, contact Techni-

cal Support.