PIC16LF18323-ESLASHP datasheet(5/442 Pages) MICROCHIP

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TABLE 1:

8-PIN ALLOCATION TABLE (PIC16(L)F18313)

RA0

ANA0

—

C1IN0+

—

DAC1OUT

MDCIN1(1)

—

CLCIN3(1)

—

IOC

ICDDAT/

ICSPDAT

RA1

ANA1

VREF+

C1IN0-

—

DAC1REF+MDMIN(1)

——

—

SCK(1)

SCL(1,3,4)

RX(1))

DT(1,3)

CLCIN2(1)

—

IOC

ICDCLK/

ICSPCLK

RA2

ANA2

VREF-

—

DAC1REF-

—

T0CKI(1)

—

CWG1IN(1) SDA(1,3,4)

SDI(1)

—

INT(1)

IOC

—

RA3

——

—

SS(1)

—

CLCIN0(1)

—

IOC

MCLR

VPP

RA4

ANA4

—

C1IN1-

—

T1G(1)

SOSCO

—

IOC

CLKOUT

OSC2

RA5

ANA5

——

—

MDCIN2(1)

T1CKI(1)

SOSCIN

SOSCI

CCP1(1)

CCP2(1)

——

—

CLCIN1(1)

—

IOC

CLKIN

OSC1

VDD

—

VDD

VSS

——

—

VSS

OUT(2)

—

C1OUT

NCO

—

DSM

TMR0

CCP1

PWM5

CWG1A

SDA(3)

CLC1OUT

CLKR

—

——

—

CCP2

PWM6

CWG1B

SCL(3)

DT(3)

CLC2OUT

——

—

CWG1C

SDO

—

——

—

CWG1D

SCK

——

—

Note

Default peripheral input. Input can be moved to any other pin with the PPS input selection registers. See Register 12-1.

All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output selection registers. See Register 12-2.

These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.

These pins are configured for I2C™ logic levels as described in Section 12.3 “Bidirectional Pins”; clock and data signals may be assigned to any of these pins. Assignments to the other pins (e.g.,

RA5) will operate, but logic levels will be standard TTL/ST as selected by the INLVL register.

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