PIC16LF18323-ESLASHP datasheet(99/442 Pages) MICROCHIP

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 2015 Microchip Technology Inc.

Preliminary

DS40001799A-page 99

PIC16(L)F18313/18323

8.0

POWER-SAVING OPERATION

MODES

The purpose of the Power-Down modes is to reduce

power consumption. There are two Power-Down

modes: Doze mode and Sleep mode.

8.1

Doze Mode

Doze mode allows for power savings by reducing CPU

operation and program memory access, without

affecting peripheral operation. Doze mode differs from

Sleep mode because the system oscillators continue to

operate, while only the CPU and program memory are

affected. The reduced execution saves power by

eliminating unnecessary operations within the CPU

and memory.

When the Doze Enable (DOZEN) bit is set (DOZEN =

), the CPU executes only one instruction cycle out of

every N cycles as defined by the DOZE<2:0> bits of the

CPUDOZE register. For example, if DOZE<2:0> = 100,

the instruction cycle ratio is 1:32. The CPU and

memory execute for one instruction cycle and then lay

idle for 31 instruction cycles. During the unused cycles,

the peripherals continue to operate at the system clock

speed.

FIGURE 8-1:

DOZE MODE OPERATION EXAMPLE

8.1.1

DOZE OPERATION

The Doze operation is illustrated in Figure 8-1. For this

example:

• Doze enable (DOZEN) bit set (DOZEN = 1)

•DOZE<2:0> = 001 (1:4) ratio

• Recover-on-Interrupt (ROI) bit set (ROI = 1)

As with normal operation, the program memory fetches

for the next instruction cycle. The Q-clocks to the

peripherals continue throughout.

System

Clock

CPU Clock

PFM Op’s

CPU Op’s

1111111111111

1234

2222

33333

4444

3333333333333

Fetch

Exec

(1,2)

Exec

Push

NOP

0004h

Interrupt

Here

(ROI = 1)

Note 1: Multi-cycle instructions are executed to completion before fetching 0004h.

2: If the pre-fetched instruction clears GIE, the ISR will not occur, but DOZEN is still cleared and the CPU will resume execution at full speed.

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