PIC16LF18323-ESLASHP datasheet(59/442 Pages) MICROCHIP

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Preliminary

DS40001799A-page 59

PIC16(L)F18313/18323

5.3

Low-Power Brown-Out Reset

(LPBOR)

The Low-Power Brown-Out Reset (LPBOR) is an

essential part of the Reset subsystem. Refer to

Figure 5-1 to see how the BOR interacts with other

modules.

The LPBOR is used to monitor the external VDD pin.

When too low of a voltage is detected, the device is

held in Reset. When this occurs, a register bit (BOR) is

changed to indicate that a BOR Reset has occurred.

The same bit is set for both the BOR and the LPBOR.

Refer to Register 5-2.

5.3.1

ENABLING LPBOR

The LPBOR is controlled by the LPBOR bit of

Configuration Words. When the device is erased, the

LPBOR module defaults to disabled.

5.3.1.1

LPBOR Module Output

The output of the LPBOR module is a signal indicating

whether or not a Reset is to be asserted. This signal is

OR’d together with the Reset signal of the BOR

module to provide the generic BOR signal, which goes

to the PCON register and to the power control block.

5.4

MCLR

The MCLR is an optional external input that can reset

the device. The MCLR function is controlled by the

MCLRE bit of Configuration Words and the LVP bit of

Configuration Words (Table 5-2).

5.4.1

MCLR ENABLED

When MCLR is enabled and the pin is held low, the

device is held in Reset. The MCLR pin is connected to

VDD through an internal weak pull-up.

The device has a noise filter in the MCLR Reset path.

The filter will detect and ignore small pulses.

5.4.2

MCLR DISABLED

When MCLR is disabled, the pin functions as a general

purpose input and the internal weak pull-up is under

software control. See Section 11.1 “I/O Priorities” for

more information.

5.5

Watchdog Timer (WDT) Reset

The Watchdog Timer generates a Reset if the firmware

does not issue a CLRWDT instruction within the time-out

period. The TO and PD bits in the STATUS register, as

well as the RWDT bit in the PCON register, are changed

to indicate the WDT Reset. See Section 9.0, Watchdog

Timer (WDT) for more information.

5.6

RESET

Instruction

A RESET instruction will cause a device Reset. The RI

bit in the PCON register will be set to ‘0’. See Table 5-4

for default conditions after a RESET instruction has

occurred.

5.7

Stack Overflow/Underflow Reset

The device can reset when the Stack Overflows or

Underflows. The STKOVF or STKUNF bits of the PCON

enabled by setting the STVREN bit in Configuration

Words.

See

Section 3.4.2

“Overflow/Underflow

Reset”

for more information.

5.8

Programming Mode Exit

Upon exit of Programming mode, the device will

behave as if a POR device Reset had just occurred.

5.9

Power-Up Timer

The Power-up Timer provides a nominal 64 ms

time-out on POR or Brown-out Reset.

The device is held in Reset as long as PWRT is active.

The PWRT delay allows additional time for the VDD to

rise to an acceptable level. The Power-up Timer is

enabled by clearing the PWRTE bit in Configuration

Words.

The Power-up Timer starts after the release of the POR

and BOR.

For additional information, refer to Application Note

AN607, “Power-up Trouble Shooting” (DS00607).

TABLE 5-2:

MCLR CONFIGURATION

MCLRE

LVP

MCLR

Disabled

Enabled

Note:

A Reset does not drive the MCLR pin low.

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