PIC16LF18323-ESLASHP datasheet(100/442 Pages) MICROCHIP

100 / 442 page

PIC16(L)F18313/18323

DS40001799A-page 100

Preliminary

 2015 Microchip Technology Inc.

8.1.2

INTERRUPTS DURING DOZE

If an interrupt occurs and the Recover-on-Interrupt bit

is clear (ROI = 0) at the time of the interrupt, the Inter-

rupt Service Routine (ISR) continues to execute at the

rate selected by DOZE<2:0>. Interrupt latency is

extended by the DOZE<2:0> ratio.

If an interrupt occurs and the ROI bit is set (ROI = 1) at

the time of the interrupt, the DOZEN bit is cleared and

the CPU executes at full speed. The prefetched instruc-

tion is executed and then the interrupt vector sequence

is executed. In Figure 8-1, the interrupt occurs during

the second instruction cycle of the Doze period, and

immediately brings the CPU out of Doze. If the

Doze-On-Exit (DOE) bit is set (DOE = 1) when the

RETFIE operation is executed, DOZEN is set, and the

CPU executes at the reduced rate based on the

DOZE<2:0> ratio.

8.2

Sleep Mode

Sleep mode is entered by executing the SLEEP

instruction, while the Idle Enable (IDLEN) bit of the

CPUDOZE register is clear (IDLEN = 0). If the SLEEP

instruction is executed while the IDLEN bit is set

(IDLEN = 1), the CPU will enter the IDLE mode

(Section 8.2.3 “Low-Power Sleep Mode”).

Upon entering Sleep mode, the following conditions

exist:

WDT will be cleared but keeps running if

enabled for operation during Sleep.

The PD bit of the STATUS register is cleared.

The TO bit of the STATUS register is set.

The CPU clock is disabled.

31 kHz LFINTOSC, HFINTOSC and SOSC are

unaffected and peripherals using them may

continue operation in Sleep.

Timer1 and peripherals that use it continue to

operate in Sleep when the Timer1 clock source

selected is:

•LFINTOSC

•T1CKI

• Secondary Oscillator

ADC is unaffected if the dedicated ADCRC

oscillator is selected.

I/O ports maintain the status they had before

SLEEP

was executed (driving high, low, or

high-impedance).

Resets other than WDT are not affected by

Sleep mode.

Refer to individual chapters for more details on

peripheral operation during Sleep.

To minimize current consumption, the following

conditions should be considered:

- I/O pins should not be floating

- External circuitry sinking current from I/O pins

- Internal circuitry sourcing current from I/O

pins

- Current draw from pins with internal weak

pull-ups

- Modules using any oscillator

I/O pins that are high-impedance inputs should be

pulled to VDD or VSS externally to avoid switching

currents caused by floating inputs.

Examples of internal circuitry that might be sourcing

current include modules such as the DAC and FVR

modules. See Section 23.0 “5-Bit Digital-to-Analog

Converter (DAC1) Module”

and Section 15.0 “Fixed

Voltage Reference (FVR)”

for more information on

these modules.

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