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WM8994ECS/R 数据表(PDF) 256 Page - Cirrus Logic

部件名 WM8994ECS/R
功能描述  Multi-channel Audio Hub CODEC for Smartphones
PDF  363 Pages
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制造商  CIRRUS [Cirrus Logic]
网页  http://www.cirrus.com
标志 CIRRUS - Cirrus Logic

WM8994ECS/R 数据表(HTML) 256 Page - Cirrus Logic

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WM8994
256
Rev 4.6
REG
NAME
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DEFAULT
R12796
(31FCh)
Write Sequencer 508
0
0
WSEQ_ADDR127 [13:0]
0000h
R12797
(31FDh)
Write Sequencer 509
0
0
0
0
0
0
0
0
WSEQ_DATA127 [7:0]
0000h
R12798
(31FEh)
Write Sequencer 510
0
0
0
0
0
WSEQ_DATA_WIDTH12
7 [2:0]
0
0
0
0
WSEQ_DATA_START127 [3:0]
0000h
R12799
(31FFh)
Write Sequencer 511
0
0
0
0
0
0
0
WSEQ
_EOS1
27
0
0
0
0
WSEQ_DELAY127 [3:0]
0000h
REGISTER BITS BY ADDRESS
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
R0 (00h)
Software
Reset
15:0
SW_RESET
[15:0]
0000_0000
_0000_000
0
Writing to this register resets all registers to their default
state. (Note - Control Write Sequencer registers are not
affected by Software Reset.)
Reading from this register will indicate device family ID
8994h.
Register 00h Software Reset
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
R1 (01h)
Power
Management
(1)
13
SPKOUTR_ENA
0
SPKMIXR Mixer, SPKRVOL PGA and SPKOUTR Output
Enable
0 = Disabled
1 = Enabled
12
SPKOUTL_ENA
0
SPKMIXL Mixer, SPKLVOL PGA and SPKOUTL Output
Enable
0 = Disabled
1 = Enabled
11
HPOUT2_ENA
0
HPOUT2 Output Stage Enable
0 = Disabled
1 = Enabled
9
HPOUT1L_ENA
0
Enables HPOUT1L input stage
0 = Disabled
1 = Enabled
For normal operation, this bit should be set as the first step
of the HPOUT1L Enable sequence.
8
HPOUT1R_ENA
0
Enables HPOUT1R input stage
0 = Disabled
1 = Enabled
For normal operation, this bit should be set as the first step
of the HPOUT1R Enable sequence.
5
MICB2_ENA
0
Microphone Bias 2 Enable
0 = Disabled
1 = Enabled
4
MICB1_ENA
0
Microphone Bias 1 Enable
0 = Disabled
1 = Enabled
2:1
VMID_SEL [1:0]
00
VMID Divider Enable and Select
00 = VMID disabled (for OFF mode)
01 = 2 x 40k divider (for normal operation)
10 = 2 x 240k divider (for low power standby)



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