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WM8994ECS/R 数据表(PDF) 260 Page - Cirrus Logic

部件名 WM8994ECS/R
功能描述  Multi-channel Audio Hub CODEC for Smartphones
PDF  363 Pages
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制造商  CIRRUS [Cirrus Logic]
网页  http://www.cirrus.com
标志 CIRRUS - Cirrus Logic

WM8994ECS/R 数据表(HTML) 260 Page - Cirrus Logic

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WM8994
260
Rev 4.6
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
R6 (06h)
Power
Management
(6)
5
AIF3_TRI
0
AIF3 Audio Interface tri-state
0 = AIF3 pins operate normally
1 = Tri-state all AIF3 interface pins
Note that pins not configured as AIF3 functions are not
affected by this register.
4:3
AIF3_ADCDAT_
SRC [1:0]
00
GPIO9/ADCDAT3 Source select
00 = AIF1 ADCDAT1
01 = AIF2 ADCDAT2
10 = GPIO5/DACDAT2
11 = Reserved
Note that GPIO9 must be configured as ADCDAT3. For
selection 10, the GPIO5 pin must also be configured as
DACDAT2.
2
AIF2_ADCDAT_
SRC
0
GPIO7/ADCDAT2 Source select
0 = AIF2 ADCDAT2
1 = GPIO8/DACDAT3
Note that GPIO7 must be configured as ADCDAT2. For
selection 1, the GPIO8 pin must also be configured as
DACDAT3.
1
AIF2_DACDAT_
SRC
0
AIF2 DACDAT Source select
0 = GPIO5/DACDAT2
1 = GPIO8/DACDAT3
Note that the selected source must be configured as
DACDAT2 or DACDAT3.
0
AIF1_DACDAT_
SRC
0
AIF1 DACDAT Source select
0 = DACDAT1
1 = GPIO8/DACDAT3
Note that, for selection 1, the GPIO8 pin must be configured
as DACDAT3.
Register 06h Power Management (6)
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
R21 (15h)
Input Mixer
(1)
8
IN1RP_MIXINR
_BOOST
0
IN1RP Pin (PGA Bypass) to MIXINR Gain Boost.
This bit selects the maximum gain setting of the
IN1RP_MIXINR_VOL register.
0 = Maximum gain is +6dB
1 = Maximum gain is +15dB
7
IN1LP_MIXINL_
BOOST
0
IN1LP Pin (PGA Bypass) to MIXINL Gain Boost.
This bit selects the maximum gain setting of the
IN1LP_MIXINL_VOL register.
0 = Maximum gain is +6dB
1 = Maximum gain is +15dB
6
INPUTS_CLAM
P
0
Input pad VMID clamp
0 = Clamp de-activated
1 = Clamp activated
Register 15h Input Mixer (1)



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