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WM8994ECS/R 数据表(PDF) 262 Page - Cirrus Logic |
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WM8994ECS/R 数据表(HTML) 262 Page - Cirrus Logic |
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262 / 363 page ![]() WM8994 262 Rev 4.6 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION REFER TO R27 (1Bh) Right Line Input 3&4 Volume 8 IN2_VU 0 Input PGA Volume Update Writing a 1 to this bit will cause IN2L and IN2R input PGA volumes to be updated simultaneously 7 IN2R_MUTE 1 IN2R PGA Mute 0 = Disable Mute 1 = Enable Mute 6 IN2R_ZC 0 IN2R PGA Zero Cross Detector 0 = Change gain immediately 1 = Change gain on zero cross only 4:0 IN2R_VOL [4:0] 0_1011 IN2R Volume -16.5dB to +30dB in 1.5dB steps Register 1Bh Right Line Input 3&4 Volume REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION REFER TO R28 (1Ch) Left Output Volume 8 HPOUT1_VU 0 Headphone Output PGA Volume Update Writing a 1 to this bit will update HPOUT1LVOL and HPOUT1RVOL volumes simultaneously. 7 HPOUT1L_ZC 0 HPOUT1LVOL (Left Headphone Output PGA) Zero Cross Enable 0 = Zero cross disabled 1 = Zero cross enabled 6 HPOUT1L_MUT E_N 1 HPOUT1LVOL (Left Headphone Output PGA) Mute 0 = Mute 1 = Un-mute 5:0 HPOUT1L_VOL [5:0] 10_1101 HPOUT1LVOL (Left Headphone Output PGA) Volume -57dB to +6dB in 1dB steps 00_0000 = -57dB 00_0001 = -56dB … (1dB steps) 11_1111 = +6dB Register 1Ch Left Output Volume REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION REFER TO R29 (1Dh) Right Output Volume 8 HPOUT1_VU 0 Headphone Output PGA Volume Update Writing a 1 to this bit will update HPOUT1LVOL and HPOUT1RVOL volumes simultaneously. 7 HPOUT1R_ZC 0 HPOUT1RVOL (Right Headphone Output PGA) Zero Cross Enable 0 = Zero cross disabled 1 = Zero cross enabled 6 HPOUT1R_MUT E_N 1 HPOUT1RVOL (Right Headphone Output PGA) Mute 0 = Mute 1 = Un-mute 5:0 HPOUT1R_VOL [5:0] 10_1101 HPOUT1RVOL (Right Headphone Output PGA) Volume -57dB to +6dB in 1dB steps 00_0000 = -57dB 00_0001 = -56dB … (1dB steps) 11_1111 = +6dB Register 1Dh Right Output Volume |
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