PCF8563

All information provided in this document is subject to legal disclaimers.

© NXP Semiconductors N.V. 2015. All rights reserved.

Product data sheet

Rev. 11 — 26 October 2015

29 of 45

NXP Semiconductors

PCF8563

Real-time clock/calendar

[1]

For reliable oscillator start-up at power on use VDD greater than 1.3 V. If powered up at 1.0 V the oscillator will start but it might be a bit

slow, especially if at high temperature. Normally the power supply is not 1.0 V at start up and only comes at the end of battery discharge.

VDD min of 1.0 V is specified so that the customer can calculate how large a battery or capacitor they need for their application. VDD min

of 1.3 V or greater is needed to ensure speedy oscillator start-up time.

[2]

Timer source clock = 1⁄60 Hz, level of pins SCL and SDA is VDD or VSS.

[3]

Tested on sample basis.

Outputs

IOL

LOW-level

output current

output sink current;

VOL =0.4 V; VDD =5V

on pin SDA

3

-

-

mA

on pin INT

1-

-

mA

on pin CLKOUT

1

-

-

mA

ILO

output leakage

current

VO =VDD or VSS

10

+1

A

Voltage detector

Vlow

low voltage

Tamb =25 C; sets bit VL; see Figure 6

-0.9

1.0

V

Table 29.

Static characteristics …continued

VDD = 1.8 V to 5.5 V; VSS =0V; Tamb = 40 C to +85 C; fosc = 32.768 kHz; quartz Rs =40 k; CL = 8 pF; unless otherwise

specified.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Tamb =25 C; Timer = 1 minute.

Tamb =25 C; Timer = 1 minute.

Fig 23. Supply current IDD as a function of supply

voltage VDD; CLKOUT disabled

Fig 24. Supply current IDD as a function of supply

voltage VDD; CLKOUT = 32 kHz

02

6

mgr888

4

VDD (V)

1

0

0.4

0.2

0.8

0.6

IDD

(

μA)

02

6

mgr889

4

VDD (V)

1

0

0.4

0.2

0.8

0.6

IDD

(

μA)