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Within 1/fS

t(DACDLY2)

(32/fS)

Normal Data

VCOM

(0.5 VCC)

Undefined

Data

Normal Data

Synchronous

Asynchronous

Synchronous

Resynchronization

Synchronization Lost

DAC VOUT

State of Synchronization

T0020-03

Normal Data(1)

Zero Data

Normal Data

ADC DOUT

t(ADCDLY2)

(32/fS)

Undefined

Data

ZERO FLAG OUTPUT: PCM3002 ONLY

OPERATIONAL CONTROL

PCM3002

PCM3003

SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004

(1)

The HPF transient response (exponentially attenuated signal from

±0.2% dc of FSR with 200-ms time constant)

appears initially.

Figure 48. DAC Output and ADC Output for Loss of Synchronization

Pin 16 is an open-drain output, used as the infinite zero detection flag on the PCM3002 only. When input data is

continuously zero for 65,536 BCKIN cycles, ZFLG is LOW; otherwise, ZFLG is in a high-impedance state.

The PCM3002 can be controlled in a software mode with a three-wire serial interface on MC (pin 18),

MD (pin 17), and ML (pin 8). Table 2 indicates selectable functions, and Figure 49 and Figure 50 illustrate the

control data input format and timing. The PCM3003 only allows for control of 16/20-bit data format, digital

de-emphasis, and power-down control by hardware pins.

Table 2. Selectable Functions (O = User Selectable; X = Not Available)

FUNCTION

ADC/DAC

PCM3002

PCM3003

Audio data format

ADC/DAC

Four selectable formats

Two selectable formats

LRCIN polarity

ADC/DAC

O

X

Loopback control

ADC/DAC

O

X

Left-channel attenuation

DAC

O

X

Right-channel attenuation

DAC

O

X

Attenuation control

DAC

O

X

Infinite zero detection and mute

DAC

O

X

DAC output control

DAC

O

X

Soft mute control

DAC

O

X

De-emphasis (OFF, 32 kHz, 44.1 kHz, 48 kHz)

DAC

O

O

ADC power-down control

ADC

O

O

DAC power-down control

DAC

O

O

High-pass filter operation

ADC

O

X

25