PCM3003 datasheet(29/42 Pages) TI2

29 / 42 page

www.ti.com

PCM3002

PCM3003

SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004

A[1:0]

Bits 10, 9: Register address

These bits define the address for register 2:

PDAD:

Bit 8: ADC power-down control

This bit places the ADC section in the lowest power-consumption mode. The ADC operation is

stopped by cutting the supply current to the ADC section, and DOUT is fixed to zero during ADC

power-down mode enable. Figure 46 illustrates the ADC DOUT response for ADC power-down

ON/OFF. This does not affect the DAC operation.

PDAD

DAC POWER-DOWN STATUS

Power-down mode disabled (default)

Power-down mode enabled

BYPS:

Bit 7: ADC high-pass filter bypass control

This bit enables or disables the high-pass filter for the ADC.

BYPS

FILTER BYPASS STATUS

High-pass filter enabled (default)

High-pass filter disabled (bypassed)

PDDA:

Bit 6: DAC power-down control

This bit places the DAC section in the lowest power-consumption mode. The DAC operation is

stopped by cutting the supply current to the DAC section, and VOUT is fixed to GND during DAC

power-down mode enable. Figure 46 illustrates the DAC VOUT response for DAC power-down

ON/OFF. This does not affect the ADC operation.

PDDA

ADC POWER-DOWN STATUS

Power-down mode disabled (default)

Power-down mode enabled

ATC:

Bit 5: DAC attenuation data mode control

When set to 1, the register 0 attenuation data can be used for both DAC channels. In this case, the

ATC

ATTENUATION CONTROL

Individual channel attenuation data control (default)

Common channel attenuation data control

IZD:

Bit 4: DAC infinite zero detection and mute control

This bit enables the infinite zero detection circuit in the PCM3002. When enabled, this circuit

disconnects the analog output amplifier from the delta-sigma DAC when the input is continuously

zero for 65,536 consecutive cycles of BCKIN.

IZD

INFINITE ZERO DETECT STATUS

Infinite zero detection and mute control disabled (default)

Infinite zero detection and mute control enabled

OUT:

Bit 3: DAC output enable control

When set to 1, the outputs are forced to V

CC/2 (bipolar zero). In this case, all registers in the

PCM3002 hold the present data. Therefore, when set to 0, the outputs return to the previous

programmed state.

OUT

DAC OUTPUT STATUS

DAC outputs enabled (default normal operation)

DAC outputs disabled (forced to BPZ)

PCM3003 数据表(PDF) 29 Page - Texas Instruments

PCM3003 数据表(HTML) 29 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42

数据表下载