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THEORY OF OPERATION

ADC SECTION

DAC SECTION

1st

SW-CAP

Integrator

Analog

In

X(z)

+

−

+

−

2nd

SW-CAP

Integrator

3rd

SW-CAP

Integrator

+

−

4th

SW-CAP

Integrator

+

+

+

+

+

+

+

+

5th

SW-CAP

Integrator

Digital

Out

Y(z)

Comparator

Qn(z)

H(z)

1-Bit

DAC

STF(z) = H(z) / [1 + H(z)]

NTF(z) = 1 / [1 + H(z)]

Y(z) = STF(z) * X(z) + NTF(z) * Qn(z)

Signal Transfer Function

Noise Transfer Function

B0005-01

PCM3002

PCM3003

SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004

The PCM3002/3003 ADC consists of two reference circuits, a stereo single-to-differential converter, a fully

differential fifth-order delta-sigma modulator, a decimation filter (including digital high pass), and a serial interface

circuit. The block diagram in this data sheet illustrates the architecture of the ADC section, Figure 40 shows the

single-to-differential converter, and Figure 52 illustrates the architecture of the fifth-order delta-sigma modulator

and transfer functions.

An internal reference circuit with three external capacitors provides all reference voltages required by the ADC,

which defines the full-scale range for the converter. The internal single-to-differential voltage converter saves the

space and extra parts needed for the external circuitry required by many delta-sigma converters. The internal

full-differential signal processing architecture provides a wide dynamic range and excellent power supply

rejection performance. The input signal is sampled at a 64

× oversampling rate, eliminating the need for a

sample-and-hold circuit, and simplifying antialias filtering requirements. The fifth-order delta-sigma noise shaper

consists of five integrators which use a switched-capacitor topology, a comparator, and a feedback loop

consisting of a one-bit DAC. The delta-sigma modulator shapes the quantization noise, shifting it out of the audio

band in the frequency domain. The high order of the modulator enables it to randomize the modulator outputs,

reducing idle tone levels.

The 64-fS, one-bit data stream from the modulator is converted to 1-fS, 16/20-bit data words by the decimation

filter, which also acts as a low-pass filter to remove the shaped quantization noise. The dc components are

removed by a high-pass filter function contained within the decimation filter.

The delta-sigma DAC section of the PCM3002/3003 is based on a 5-level amplitude quantizer and a third-order

noise shaper. This section converts the oversampled input data to a 5-level delta-sigma format. A block diagram

of the 5-level delta-sigma modulator is shown in Figure 53. This 5-level delta-sigma modulator has the advantage

of improved stability and reduced clock-jitter sensitivity over the typical one-bit (2-level) delta-sigma modulator.

The combined oversampling rate of the delta-sigma modulator and the internal 8

× interpolation filter is 64 f

S for a

256-fS system clock. The theoretical quantization noise performance of the 5-level delta-sigma modulator is

shown in Figure 54.

Figure 52. Simplified Fifth-Order Delta-Sigma Modulator

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