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VREF2

20

19

18

17

16

15

14

13

5

6

7

8

9

10

11

12

VINL

RST/PDAD

ML/PDDA

SYSCLK

LRCIN

BCKIN

DOUT

VOUTR

DGND

VOUTL

MC/DEM0

MD/DEM1

ZFLG/20BIT

VDD

DIN

Rch In

Audio

Interface

VCC1

24

23

22

21

1

2

3

4

VCC1

VINR

VREF1

VCC2

AGND1

AGND2

VCOM

+

+

0.1

µF

and 10

µF(1)

MC(6)/DEM0(7)

ZFLG(6)/20BIT(7)

Control

Interface

PCM3002/3003

+

+

1

µF(3)

4.7

µF(2)

4.7

µF(2)

Lch In

+

1

µF(3)

SYSCLK

L/R CLK

BIT CLK

DATA OUT

DATA IN

S0014-01

+3 V Analog VCC

+

+

0.1

µF

and 10

µF(1)

4.7

µF(2)

+

4.7

µF(4)

Rch Out(5)

Lch Out(5)

MD(6)/DEM1(7)

0.1

µF

and 10

µF(1)

ML(6)/PDDA(7)

RST(6)/PDAD(7)

4.7

µF(4)

10 k

Ω

+

PCM3002

PCM3003

SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004

(1)

0.1-

µF ceramic and 10-µF tantalum, typical, depending on power supply quality and pattern layout

(2)

4.7-

µF, typical, gives settling time with 30-ms (4.7 µF × 6.4 kΩ) time constant in the power ON and power-down OFF

periods.

(3)

1-

µF, typical, gives 5.3-Hz cutoff frequency for the input HPF in normal operation and gives settling time with 30-ms

(1

µF × 30 kΩ) time constant in the power ON and power-down OFF periods.

(4)

4.7-

µF, typical, gives 3.4-Hz cutoff frequency for the output HPF in normal operation and gives settling time with

47-ms (4.7

µF × 10 kΩ) time constant in the power ON and power-down OFF periods.

(5)

Post low-pass filter with RIN > 10 kΩ, depending on system performance requirements

(6)

MC, MD, ML, ZFLG, RST, and 10-k

Ω pullup resistor are for the PCM3002.

(7)

DEM0, DEM1, 20BIT, PDAD, PDDA are for the PCM3003.

Figure 51. Typical Connection Diagram for PCM3002/3003

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