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APPLICATION AND LAYOUT CONSIDERATIONS

POWER-SUPPLY BYPASSING

GROUNDING

VOLTAGE INPUT

VREF INPUTS

VCOM INPUT

SYSTEM CLOCK

RESET CONTROL

EXTERNAL MUTE CONTROL

TYPICAL CONNECTION DIAGRAM

PCM3002

PCM3003

SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004

The digital and analog power supply lines to PCM3002/3003 should be bypassed to the corresponding ground

pins with both 0.1-

µF ceramic and 10-µF tantalum capacitors as close to the device pins as possible. Although

the PCM3002/3003 has three power-supply lines to optimize dynamic performance, the use of one common

power supply is generally recommended to avoid unexpected latch-up or pop noise due to power-supply

sequencing problems. If separate power supplies are used, back-to-back diodes are recommended to avoid

latch-up problems.

In order to optimize the dynamic performance of the PCM3002/3003, the analog and digital grounds are not

connected internally. The PCM3002/3003 performance is optimized with a single ground plane for all returns. It is

recommended to tie all PCM3002/3003 ground pins to the analog ground plane using low-impedance

connections. The PCM3002/3003 should reside entirely over this plane to avoid coupling high-frequency digital

switching noise into the analog ground plane.

A tantalum or aluminum electrolytic capacitor, between 1

µF and 10 µF, is recommended as an ac-coupling

capacitor at the inputs. Combined with the 30-k

Ω characteristic input impedance, a 1-µF coupling capacitor

establishes a 5.3-Hz cutoff frequency for blocking dc. The input voltage range can be increased by adding a

series resistor on the analog input line. This series resistor, when combined with the 30-k

Ω input impedance,

creates a voltage divider and enables larger input ranges.

A 4.7-

µF to 10-µF tantalum capacitor is recommended between V

REF1, VREF2, and AGND1 to ensure low source

impedance for the ADC references. These capacitors should be located as close as possible to the reference

pins to reduce dynamic errors on the ADC reference.

A 4.7-

µF to 10-µF tantalum capacitor is recommended between V

COM and AGND1 to ensure low source

impedance of the ADC and DAC common voltage. This capacitor should be located as close as possible to the

VCOM pin to reduce dynamic errors on the dc common-mode voltage.

The quality of the system clock can influence dynamic performance of both the ADC and DAC in the

PCM3002/3003. The duty cycle and jitter at the system-clock input pin should be carefully managed. When

power is supplied to the part, the system clock, bit clock (BCKIN), and word clock (LCRIN) also must be supplied

simultaneously. Failure to supply the audio clocks results in a power-dissipation increase of up to three times

normal dissipation and can degrade long-term reliability if the maximum power-dissipation limit is exceeded.

If capacitors larger than 22

µF are used on V

REF and VCOM, external reset control (RST = low for the PCM3002,

PDAD = low and PDDA = low for the PCM3003) is required after the VREF, VCOM transient response is settled.

For power-down ON/OFF control without click noise, which is generated by a DC level change on the DAC

output, use of the external mute control is recommended. The control sequence, which is external mute ON,

codec power-down ON, SYSCLK stop and resume if necessary, codec power-down OFF, and external mute

OFF is recommended.

A typical connection diagram for the PCM3002/3003 is shown in Figure 51.

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