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XCVU5P 数据表(PDF) 21 Page - Advanced Micro Devices

部件名 XCVU5P
功能描述  Virtex UltraScale FPGA Data Sheet: DC and AC Switching Characteristics
PDF  68 Pages
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制造商  AMD [Advanced Micro Devices]
网页  http://www.amd.com
标志 AMD - Advanced Micro Devices

XCVU5P 数据表(HTML) 21 Page - Advanced Micro Devices

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FPGA Logic Switching Characteristics
The following IOB high-performance (HP) table summarizes the values of standard-specific data input delay
adjustments, output delays terminating at pads (based on standard) and 3-state delays.
• TINBUF_DELAY_PAD_I is the delay from IOB pad through the input buffer to the I-pin of an IOB pad. The delay
varies depending on the capability of the SelectIO input buffer.
• TOUTBUF_DELAY_O_PAD is the delay from the O pin to the IOB pad through the output buffer of an IOB pad.
The delay varies depending on the capability of the SelectIO output buffer.
• TOUTBUF_DELAY_TD_PAD is the delay from the T pin to the IOB pad through the output buffer of an IOB pad,
when 3-state is disabled. The delay varies depending on the SelectIO capability of the output buffer. In I/O
banks, the internal DCI termination turn-on time is always faster than TOUTBUF_DELAY_TD_PAD when the
DCITERMDISABLE pin is used.
IOB High Performance (HP) Switching Characteristics
Table 24: IOB High Performance (HP) Switching Characteristics
I/O Standards
TINBUF_DELAY_PAD_I
TOUTBUF_DELAY_O_PAD
TOUTBUF_DELAY_TD_PAD
Units
0.90V
0.85V
0.72V
0.90V
0.85V
0.72V
0.90V
0.85V
0.72V
-3
-2
-1
-2
-3
-2
-1
-2
-3
-2
-1
-2
DIFF_HSTL_I_12_F
0.288
0.394 0.402
0.394
0.410
0.423 0.443
0.423
0.514
0.553
0.582
0.553
ns
DIFF_HSTL_I_12_M
0.288
0.394 0.402
0.394
0.552
0.552 0.583
0.552
0.632
0.641
0.679
0.641
ns
DIFF_HSTL_I_12_S
0.288
0.394 0.402
0.394
0.752
0.752 0.800
0.752
0.813
0.813
0.868
0.813
ns
DIFF_HSTL_I_18_F
0.259
0.319 0.339
0.319
0.439
0.456 0.474
0.456
0.549
0.576
0.606
0.576
ns
DIFF_HSTL_I_18_M
0.259
0.319 0.339
0.319
0.563
0.570 0.603
0.570
0.636
0.653
0.692
0.653
ns
DIFF_HSTL_I_18_S
0.259
0.319 0.339
0.319
0.782
0.782 0.834
0.782
0.816
0.816
0.871
0.816
ns
DIFF_HSTL_I_DCI_12_F
0.288
0.394 0.402
0.394
0.393
0.406 0.429
0.406
0.502
0.534
0.564
0.534
ns
DIFF_HSTL_I_DCI_12_M
0.288
0.394 0.402
0.394
0.546
0.557 0.587
0.557
0.636
0.653
0.694
0.653
ns
DIFF_HSTL_I_DCI_12_S
0.288
0.394 0.402
0.394
0.755
0.755 0.806
0.755
0.842
0.842
0.907
0.842
ns
DIFF_HSTL_I_DCI_18_F
0.259
0.323 0.339
0.323
0.422
0.445 0.461
0.445
0.509
0.566
0.595
0.566
ns
DIFF_HSTL_I_DCI_18_M
0.259
0.323 0.339
0.323
0.546
0.555 0.586
0.555
0.626
0.643
0.684
0.643
ns
DIFF_HSTL_I_DCI_18_S
0.259
0.323 0.339
0.323
0.762
0.762 0.818
0.762
0.836
0.836
0.900
0.836
ns
DIFF_HSTL_I_DCI_F
0.335
0.397 0.417
0.397
0.407
0.431 0.445
0.431
0.517
0.555
0.575
0.555
ns
DIFF_HSTL_I_DCI_M
0.335
0.397 0.417
0.397
0.549
0.553 0.583
0.553
0.634
0.644
0.684
0.644
ns
DIFF_HSTL_I_DCI_S
0.335
0.397 0.417
0.397
0.767
0.767 0.823
0.767
0.848
0.848
0.912
0.848
ns
DIFF_HSTL_I_F
0.304
0.404 0.417
0.404
0.409
0.423 0.443
0.423
0.514
0.549
0.581
0.549
ns
DIFF_HSTL_I_M
0.304
0.404 0.417
0.404
0.549
0.555 0.586
0.555
0.624
0.640
0.677
0.640
ns
DIFF_HSTL_I_S
0.304
0.404 0.417
0.404
0.767
0.767 0.818
0.767
0.811
0.811
0.866
0.811
ns
DIFF_HSUL_12_DCI_F
0.320
0.381 0.400
0.381
0.411
0.425 0.443
0.425
0.520
0.558
0.586
0.558
ns
DIFF_HSUL_12_DCI_M
0.320
0.381 0.400
0.381
0.546
0.557 0.587
0.557
0.636
0.653
0.694
0.653
ns
DIFF_HSUL_12_DCI_S
0.320
0.381 0.400
0.381
0.737
0.737 0.787
0.737
0.822
0.822
0.885
0.822
ns
DIFF_HSUL_12_F
0.322
0.394 0.402
0.394
0.394
0.412 0.430
0.412
0.494
0.538
0.566
0.538
ns
DIFF_HSUL_12_M
0.322
0.394 0.402
0.394
0.552
0.552 0.583
0.552
0.632
0.641
0.679
0.641
ns
DIFF_HSUL_12_S
0.322
0.394 0.402
0.394
0.752
0.752 0.800
0.752
0.813
0.813
0.868
0.813
ns
Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics
DS923 (v1.10) April 26, 2019
www.xilinx.com
Product Specification
21
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