XCVU5P datasheet(67/68 Pages) AMD

67 / 68 page

Date

Version

Description of Revisions

04/09/2018

1.6

Added the XCVU31P, XCVU33P, XCVU35P, and XCVU37P devices throughout the data sheet. Added the

specifications for High Bandwidth Memory to Table 1, Table 2, Table 5, the Power-On/Off Power Supply

Sequencing section, Table 6, Table 7, and Table 73.

Updated Table 16, Table 17, and Table 18 to production release the following devices in Vivado Design

Suite 2018.1 v1.19.

XCVU3P: -3E (VCCINT = 0.90V)

XCVU5P: -3E (VCCINT = 0.90V)

XCVU7P: -3E (VCCINT = 0.90V)

XCVU9P: -3E (VCCINT = 0.90V)

Added Table 38 and Table 41. Added Note 2 and Note 3 to Table 40. Revised Table 70 to add specifc mode

specifications and remove Note 1. Added Table 72.

02/07/2018

1.5

Updated Table 16, Table 17, and Table 18 to production release the following devices in Vivado Design

Suite 2017.4.1 v1.18.

XCVU11P: -3E (VCCINT = 0.90V)

XCVU13P: -3E (VCCINT = 0.90V)

Revised some of the -3E (VCCINT = 0.90V) speed files in Table 35, Table 36, Table 37, and Table 39.

Revised the DVPPOUT control signal in Table 43.

11/28/2017

1.4

In Table 1, corrected the minimum voltage for the System Monitor section.

Updated Table 16, Table 17, and Table 18 to production release all the -2LE (VCCINT = 0.85V) and -2LE

(VCCINT = 0.72V) devices/speed/temperature grades in Vivado Design Suite 2017.3.1.

Revised the FREFCLK descriptions in Table 30.

Revised some of the -3E and -2LE (VCCINT = 0.72V) speed files in Table 35, Table 36, Table 37, Table 39, and

added package values to Table 42.

Revised the FGTYQRANGE2 -1 speed grade minimum in Table 46. Added TSPICCM2 and TSPICCFC2 to Table 77.

10/02/2017

1.3

Updated Table 1 to include maximum TSOL

Updated Table 16, Table 17, and for dry rework and reflow soldering.Table 18 to production release the

following devices/speed/temperature grades in Vivado Design Suite 2017.2.1.

XCVU11P: -2E, -2I, -1E, -1I

XCVU13P: -2E, -2I, -1E, -1I

In Table 24, revised the TOUTBUF_DELAY_O_PAD -2 (VCCINT for dry r = 0.85V) values for DIFF_SSTL135_S,

DIFF_SSTL15_DCI_S, DIFF_SSTL15_S, DIFF_SSTL18_I_DCI_S, and DIFF_SSTL18_I_S.

Revised some of the -3E and -2LE (VCCINT = 0.72V) speed files in Table 24, Table 35, Table 36, and Table 37.

06/27/2017

1.2

Updated Table 16, Table 17, and Table 18 to production release the following devices/speed/temperature

grades in Vivado Design Suite 2017.2.

XCVU5P: -2E, -2I, -1E, -1I

XCVU7P: -2E, -2I, -1E, -1I

XCVU9P: -2E, -2I, -1E, -1I

Updated Note 12 in Table 2 for clarity. In Table 3, removed unsupported voltages (2.5V and 3.3V) from

IRPU and IRPD. Added Note 3 to Table 23. Revised the -3E and -2LE (VCCINT = 0.72V) speed files in Table 24,

Table 25, Table 35, Table 36, Table 37, and Table 39. In Table 26 removed from the input delay

measurement methodology section the following class II I/O standards: SSTL135_II, SSTL15_II, SSTL18_II,

DIFF_SSTL135_II, DIFF_SSTL15_II and DIFF_SSTL18_II. Updated the FMAX symbol names and values in Table

29. Added Note 1 to Table 31. Added Note 3 to Table 71. In Table 77, updated the -2LE (VCCINT = 0.72V)

specifications for FMCCK, FSCCK, FEMCCK, FICAPCK, TSMDCCK/TSMCCKD, TSMCKCSO, TSMCO, FRBCCK, TBPIDCC/TBPICCD,

and TSPIDCC/TSPICCD.

04/19/2017

1.1

Updated the Summary description. In Table 1, updated Note 6, added data, and added Note 7, Note 8,

and Note 9. Updated and added data to Table 2 through Table 6.

Removed the -1LI speed grade.

Updated Table 16, Table 17, and Table 18 to production release in Vivado Design Suite 2017.1 for the

XCVU3P: -2E, -2I, -1E, -1I.

Updated Table 15. Added Note 1 to Table 17. Updated Table 19, Table 20, Table 24, Table 25, Table 26,

Table 28, Table 29, and Table 30. Added Table 21. Added MMCM_FDPRCLK_MAX to Table 33 and

PLL_FDPRCLK_MAX to Table 34. Updated to Vivado Design Suite 2017.1 Table 35, Table 36, Table 37, and

Table 39. Added data to Table 40 and Table 42. Updated the GTY Transceiver Specifications section.

Revised the Integrated Interface Block for Interlaken section. Updated the System Monitor Specifications

section adding notes to the tables. Updated the Configuration Switching Characteristics section.

Removed the eFUSE Programming Conditions table and added the specifications to Table 2 and Table 3.

Updated the Automotive Applications Disclaimer.

04/20/2016

1.0

Initial Xilinx release.

Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics

DS923 (v1.10) April 26, 2019

www.xilinx.com

Product Specification

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