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XCVU5P 数据表(PDF) 65 Page - Advanced Micro Devices

部件名 XCVU5P
功能描述  Virtex UltraScale FPGA Data Sheet: DC and AC Switching Characteristics
PDF  68 Pages
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制造商  AMD [Advanced Micro Devices]
网页  http://www.amd.com
标志 AMD - Advanced Micro Devices

XCVU5P 数据表(HTML) 65 Page - Advanced Micro Devices

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Table 77: Configuration Switching Characteristics (cont'd)
Symbol
Description
Speed Grade and VCCINT Operating Voltages
Units
0.90V
0.85V
0.72V
-3
-2
-1
-2
TTCKTDO
TCK falling edge to
TDO output
XCVU3P, XQVU3P
7.0
7.0
7.0
7.0
ns, Max
XCVU5P, XCVU7P,
XQVU7P, XCVU9P,
XCVU11P, XQVU11P,
XCVU13P, XCVU27P,
XCVU29P, XCVU31P,
XCVU33P, XCVU35P,
XCVU37P
15.0
15.0
15.0
15.0
ns, Max
FTCK
TCK frequency
XCVU3P, XQVU3P
66
66
66
66
MHz, Max
XCVU5P, XCVU7P,
XQVU7P, XCVU9P,
XCVU11P, XQVU11P,
XCVU13P, XCVU27P,
XCVU29P, XCVU31P,
XCVU33P, XCVU35P,
XCVU37P
20
20
20
20
MHz, Max
BPI Master Flash Mode Programming Switching
TBPICCO
A[28:00], RS[1:0], FCS_B, FOE_B, FWE_B, ADV_B
clock to out
10
10
10
10
ns, Max
TBPIDCC/TBPICCD
D[15:00] setup/hold
XCVU3P, XQVU3P,
XCVU5P, XCVU7P,
XQVU7P, XCVU9P
4.0/0
4.0/0
4.0/0
5.0/0
ns, Min
XCVU11P, XQVU11P,
XCVU13P, XCVU27P,
XCVU29P, XCVU31P,
XCVU33P, XCVU35P,
XCVU37P
4.5/0
4.5/0
4.5/0
8.0/0
ns, Min
SPI Master Flash Mode Programming Switching
TSPIDCC/TSPICCD
D[03:00] setup/hold
3.0/0
3.0/0
3.0/0
4.0/0
ns, Min
TSPIDCC/TSPICCD
D[07:04] setup/hold
XCVU3P, XQVU3P,
XCVU5P, XCVU7P,
XQVU7P, XCVU9P
4.0/0
4.0/0
4.0/0
5.0/0
ns, Min
XCVU11P, XQVU11P,
XCVU13P, XCVU27P,
XCVU29P, XCVU31P,
XCVU33P, XCVU35P,
XCVU37P
4.5/0
4.5/0
4.5/0
8.0/0
ns, Min
TSPICCM
MOSI clock to out
8.0
8.0
8.0
8.0
ns, Max
TSPICCM2
D[04] clock to out
10.0
10.0
10.0
10.0
ns, Max
TSPICCFC
FCS_B clock to out
8.0
8.0
8.0
8.0
ns, Max
TSPICCFC2
FCS2_B clock to out
10.0
10.0
10.0
10.0
ns, Max
DNA Port Switching
FDNACK
DNA port frequency
200
200
200
175
MHz, Max
STARTUPE3 Ports
TUSRCCLKO
STARTUPE3 USRCCLKO input port to CCLK pin
output delay
0.25/6.00
0.25/6.50
0.25/7.50
0.25/9.00
ns, Min/Max
TDO
DO[3:0] ports to D03-D00 pins output delay
0.25/6.70
0.25/7.70
0.25/8.40
0.25/10.00
ns, Min/Max
TDTS
DTS[3:0] ports to D03-D00 pins 3-state delays
0.25/6.70
0.25/7.70
0.25/8.40
0.25/10.00
ns, Min/Max
TFCSBO
FCSBO port to FCS_B pin output delay
0.25/6.90
0.25/7.50
0.25/8.40
0.25/9.80
ns, Min/Max
TFCSBTS
FCSBTS port to FCS_B pin 3-state delay
0.25/6.90
0.25/7.50
0.25/8.40
0.25/9.80
ns, Min/Max
Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics
DS923 (v1.10) April 26, 2019
www.xilinx.com
Product Specification
65
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