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STR910FAM32X6 数据表(PDF) 17 Page - STMicroelectronics |
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STR910FAM32X6 数据表(HTML) 17 Page - STMicroelectronics |
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17 / 99 page  STR91xFAx32 STR91xFAx42 STR91xFAx44 Functional overview 17/99 3.8 One-time-programmable (OTP) memory There are 32 bytes of OTP memory ideally suited for serial numbers, security keys, factory calibration constants, or other permanent data constants. These OTP data bytes can be programmed only one time through either the JTAG interface or by the CPU, and these bytes can never be altered afterwards. As an option, a “lock bit” can be set by the JTAG interface or the CPU which will block any further writing to the this OTP area. The “lock bit” itself is also OTP. If the OTP array is unlocked, it is always possible to go back and write to an OTP byte location that has not been previously written, but it is never possible to change an OTP byte location if any one bit of that particular byte has been written before. The last two OTP bytes (bytes 31 and 30) are reserved for the STR91xFA product ID and revision level. 3.8.1 Product ID and revision level OTP bytes 31 and 30 are programmed at ST factory before shipment and may be read by firmware to determine the STR91xFA product type and silicon revision so it can optionally take action based on the silicon on which it is running. In Rev H devices, byte 31 contains the the major family identifier of "9" (for STR9) in the high-nibble location and the minor family identifier in the low nibble location, which can be used to determine the size of Primary flash memory. In all devices, byte 30 contains the silicon revision level indicator. See Table 6 for values related to the revisions of STR9 production devices and size of Primary Flash memory. See Section 8 for details of external identification of silicon revisions. 3.9 Vectored interrupt controller (VIC) Interrupt management in the STR91xFA is implemented from daisy-chaining two standard ARM VIC units. This combined VIC has 32 prioritized interrupt request channels and generates two interrupt output signals to the CPU. The output signals are FIQ and IRQ, with FIQ having higher priority. 3.9.1 FIQ handling FIQ (Fast Interrupt reQuest) is the only non-vectored interrupt and the CPU can execute an Interrupt Service Routine (ISR) directly without having to determine/prioritize the interrupt source, minimizing ISR latency. Typically only one interrupt source is assigned to FIQ. An FIQ interrupt has its own set of banked registers to minimize the time to make a context switch. Any of the 32 interrupt request input signals coming into the VIC can be assigned to FIQ. Table 6. Product ID and revision level values Production salestype Silicon revision Size of Primary Flash OTP byte 31 OTP byte 30 STR91xFxxxxx Rev D 256K or 512K 91h 03h STR91xFAxxxxx Rev G 256K or 512K 91h 20h STR91xFAxxxxx Rev H 256K 90h 21h STR91xFAxxxxx Rev H 512K 91h 21h |
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