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STR910FAM32X6 数据表(PDF) 28 Page - STMicroelectronics |
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STR910FAM32X6 数据表(HTML) 28 Page - STMicroelectronics |
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28 / 99 page  Functional overview STR91xFAx32 STR91xFAx42 STR91xFAx44 28/99 Figure 3. JTAG chaining inside the STR91xFA 3.15.1 In-system-programming The JTAG interface is used to program or erase all memory areas of the STR91xFA device. The pin RESET_INn must be asserted during ISP to prevent the CPU from fetching invalid instructions while the Flash memories are being programmed. Note that the 32 bytes of OTP memory locations cannot be erased by any means once programmed by JTAG ISP or the CPU. 3.15.2 Boundary scan Standard JTAG boundary scan testing compliant with IEEE-1149.1 is available on the majority of pins of the STR91xFA for circuit board test during manufacture of the end product. STR91xFA pins that are not serviced by boundary scan are the following: ● JTAG pins JTCK, JTMS, JTDI, JTDO, JTRSTn, JRTCK ● Oscillator input pins X1_CPU, X2_CPU, X1_RTC, X2_RTC ● Tamper detect input pin TAMPER_IN (128-pin and 144-pin packages only) 3.15.3 CPU debug The ARM966E-S CPU core has standard ARM EmbeddedICE-RT logic, allowing the STR91xFA to be debugged through the JTAG interface. This provides advanced debugging features making it easier to develop application firmware, operating systems, and the hardware itself. Debugging requires that an external host computer, running debug software, is connected to the STR91xFA target system via hardware which converts the stream of debug data and commands from the host system’s protocol (USB, Ethernet, etc.) to the JTDI JTMS JTCK JTDO TDI TMS TCK TDO TDO TMS TCK TDI JTAG TAP CONTROLLER #1 JTAG TAP CONTROLLER #3 BURST FLASH MEMORY DIE ARM966ES DIE BOUNDARY SCAN STR91xx JTRSTn TRST TDI TMS TCK TDO JTAG TAP CONTROLLER #2 CPU DEBUG TRST JRTCK TRST MAIN FLASH SECONDARY FLASH JTAG Instruction register length: 5 bits for TAP #1 4 bits for TAP #2 JTAG Instruction register length is 8 bits |
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