STR910FAM32X6 datasheet(18/99 Pages) STMICROELECTRONICS

18 / 99 page

Functional overview

STR91xFAx32 STR91xFAx42 STR91xFAx44

18/99

3.9.2

IRQ handling

IRQ is a vectored interrupt and is the logical OR of all 32 interrupt request signals coming

into the 32 IRQ channels. Priority of individual vectored interrupt requests is determined by

hardware (IRQ channel Intr 0 is highest priority, IRQ channel Intr 31 is lowest).

However, inside the same VIC (primary or secondary VIC), CPU firmware may re-assign

individual interrupt sources to individual hardware IRQ channels, meaning that firmware can

effectively change interrupt priority levels as needed within the same VIC (from priority 0 to

priority 16).

Note:

VIC0 (primary VIC) interrupts always have higher priority than VIC1 (secondary VIC)

interrupts

When the IRQ signal is activated by an interrupt request, VIC hardware will resolve the IRQ

interrupt priority, then the ISR reads the VIC to determine both the interrupt source and the

vector address to jump to the service code.

The STR91xFA has a feature to reduce ISR response time for IRQ interrupts. Typically, it

requires two memory accesses to read the interrupt vector address from the VIC, but the

STR91xFA reduces this to a single access by adding a 16th entry in the instruction branch

cache, dedicated for interrupts. This 16th cache entry always holds the instruction that reads

the interrupt vector address from the VIC, eliminating one of the memory accesses typically

required in traditional ARM implementations.

3.9.3

Interrupt sources

The 32 interrupt request signals coming into the VIC on 32 IRQ channels are from various

sources; 5 from a wake-up unit and the remaining 27 come from internal sources on the

STR91xFA such as on-chip peripherals, see Table 7. Optionally, firmware may force an

interrupt on any IRQ channel.

One of the 5 interrupt requests generated by the wake-up unit (IRQ25 in Table 7) is derived

from the logical OR of all 32 inputs to the wake-up unit. Any of these 32 inputs may be used

to wake up the CPU and cause an interrupt. These 32 inputs consist of 30 external

interrupts on selected and enabled GPIO pins, plus the RTC interrupt, and the USB Resume

interrupt.

Each of 4 remaining interrupt requests generated by the wake-up unit (IRQ26 in Table 7) are

derived from groupings of 8 interrupt sources. One group is from GPIO pins P3.2 to P3.7

plus the RTC interrupt and the USB Resume interrupt; the next group is from pins P5.0 to

P5.7; the next group is from pins P6.0 to P6.7; and last the group is from pins P7.0 to P7.7.

This allows individual pins to be assigned directly to vectored IRQ interrupts or one pin

assigned directly to the non-vectored FIQ interrupt.

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