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TMP103

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SBOS545D – FEBRUARY 2011 – REVISED DECEMBER 2018

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7.5.10.2 Slave Transmitter Mode

The first byte transmitted by the master is the slave address, with the R/W bit high. The slave acknowledges

reception of a valid slave address. The next byte is transmitted by the slave of the register indicated by the

Pointer Register. The master acknowledges reception of the data byte. The master can terminate data transfer

by generating a Not-Acknowledge on reception of the data byte, or generating a START or STOP condition.

7.5.11 General Call

The TMP103 responds to a two-wire General Call address (0000000) if the eighth bit is 0. The device

acknowledges the General Call address and responds to commands in the second byte. If the second byte is

00000110, the TMP103 internal registers are reset to power-up values. The TMP103 does not support the

General Address acquire command.

7.5.12 High-Speed (Hs) Mode

For the two-wire bus to operate at frequencies greater than 400 kHz, the master device must issue an Hs-mode

master code (00001xxx) as the first byte after a START condition to switch the bus to high-speed operation. The

TMP103 does not acknowledge this byte, but switches its input filters on SDA and SCL and its output filters on

SDA to operate in Hs-mode, allowing transfers at up to 3.4 MHz. After the Hs-mode master code has been

issued, the master transmits a START condition followed by a two-wire slave address to initiate a data transfer

operation. The bus continues to operate in Hs-mode until a STOP condition occurs on the bus. Upon receiving

the STOP condition, the TMP103 switches the input and output filters back to the default fast-mode operation.

7.5.13 Timeout Function

The TMP103 resets the serial interface if SCL is held low for 30 ms (typical). The TMP103 releases the bus if it is

pulled low and waits for a START condition. To avoid activating the timeout function, it is necessary to maintain a

communication speed of at least 1 kHz for SCL operating frequency.

7.5.14 Multiple Device Access

The TMP103 supports Multiple Device Access (MDA), which allows the master to communicate with multiple

TMP103 devices on the same bus interface with one interface transaction. MDA commands consist of an MDA

read address (00000001) and an MDA write address (00000000). The device acknowledges the MDA address

and responds to the command accordingly. For the MDA to function correctly, different product versions of the

TMP103 must be used in the system; see Table 2.

7.5.14.1 Multiple Device Access Write

The master transmits an MDA write address followed by the pointer address of the register to be accessed; see

Table 4. Following the pointer, all of the TMP103 devices on the bus acknowledge and wait for the next byte of

data to be written to the addressed registers. When the data byte is received by the TMP103 devices, they store

and acknowledge the transmitted byte. The TMP103 devices store the same data on all devices on the bus in

one transaction; see Figure 4.

7.5.14.2 Multiple Device Access Read

Before an MDA read transaction can begin, the master must first send an MDA write transaction to set the

appropriate pointer address of the register to be accessed, as stated in the previous section. The master can

then transmit an MDA read address followed by a read byte for each TMP103 used on the bus. For example, if a

TMP103A and TMP103B are used on the same bus and an MDA read address is sent, the address must be

followed by two bytes of data and two master acknowledges. The TMP103A sends data on the first byte and the

TMP103B sends data on the second byte. The master must issue an acknowledge for each byte read to read all

of the TMP103 devices on the bus; see Figure 5. If the master does not acknowledge each byte of data, the

TMP103s stop sending subsequent data for any remaining devices.

Up to eight TMP103 devices can be on the same bus and respond to MDA commands; see Table 2.