XI

XO

24 MHz

CL2

R1

10 M

CL1

Copyright © 2016, Texas Instruments Incorporated

14

TUSB4041I

SLLSEK3E – JULY 2015 – REVISED SEPTEMBER 2017

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8.3.4 Clock Generation

The TUSB4041I device accepts a crystal input to drive an internal oscillator or an external clock source. If a clock

is provided to the XI pin instead of a crystal, the XO pin is left open. Otherwise, if a crystal is used, the

connection must follow these guidelines. Because the XI and XO pins are coupled to other leads and supplies on

the PCB, keep traces as short as possible and away from any switching leads. Minimize the capacitance

between the XI and XO pins by shielding C1 and C2 with the clean ground lines.

Figure 2. TUSB4041I Clock

8.3.5 Crystal Requirements

The crystal must be fundamental mode with load capacitance of 12 to 24 pF and frequency stability rating of

±100 PPM or better. To ensure proper startup oscillation condition, TI recommends a maximum crystal

equivalent series resistance (ESR) of 50 Ω. If a crystal source is used, use a parallel load capacitor. The exact

load capacitance value used depends on the crystal vendor. Refer to application note Selection and Specification

for Crystals for Texas Instruments USB 2.0 Devices (SLLA122) for details on how to determine the load

capacitance value.

8.3.6 Input Clock Requirements

When using an external clock source such as an oscillator, the reference clock should have a frequency stability

of ±100 PPM or better and have less than 50-ps absolute peak-to-peak jitter. Tie XI to the 1.8-V clock source,

and leave XO floating.

8.3.7 Power-Up and Reset

The TUSB4041I device does not have specific power-sequencing requirements with respect to the core power

(VDD) or I/O and analog power (VDD33). The core power (VDD) or I/O power (VDD33) can be powered up for an

indefinite period of time while the other is not powered up if all of the following constraints are met:

•

Observe all maximum ratings and recommended operating conditions.

•

Observe all warnings about exposure to maximum rated and recommended conditions, particularly junction

temperature. These apply to power transitions and normal operation.

•

Limit bus contention to 100 hours over the projected lifetime of the device while VDD33 is powered-up.

•

Do not exceed the ratings listed in the Absolute Maximum Ratings table for bus contention while VDD33 is

powered-down.

A supply bus is powered-up when the voltage is within the recommended operating range. A supply bus is

powered-down when it is below that range, and either stable or in transition.

The device requires a minimum reset duration of 3 ms. This reset duration is defined as the time when the power

supplies are in the recommended operating range to the deassertion of the GRSTz pin. Generate the reset pulse

using a programmable-delay supervisory device or using an RC circuit.