TUSB4041IPAP datasheet(37/48 Pages) TI2

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TUSB4041I

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SLLSEK3E – JULY 2015 – REVISED SEPTEMBER 2017

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11 Layout

11.1 Layout Guidelines

Use the layout guidelines listed in this section for proper PCB layout design.

11.1.1 Placement

•

Place a 9.53-kΩ ±1% resistor connected to pin USB_R1 as close as possible to the TUSB4041I device.

•

Place a 0.1-µF capacitor as close as possible on each VDD and VDD33 power pin.

•

The ESD and EMI protection devices (if used) should also be placed as close as possible to the USB

connector.

•

If a crystal is used, it must be placed as close as possible to the XI and XO pins of the TUSB4041I device.

•

Place voltage regulators as far away as possible from the TUSB4041I device, the crystal, and the differential

pairs.

•

In general, the user should place the large bulk capacitors associated with each power rail as close as

possible to the voltage regulators.

11.1.2 Package Specific

•

The TUSB4041I device package has a 0.5-mm pin pitch.

•

The TUSB4041I device package has a 4.64-mm × 4.64-mm thermal pad. This thermal pad must be

connected to ground through a system of vias.

•

Solder mask all vias under device, except for those connected to the thermal pad, to avoid any potential

issues with thermal pad layouts.

11.1.3 Differential Pairs

This section describes the layout recommendations for all the TUSB4041I device differential pairs: USB_DP_XX,

USB_DM_XX.

•

The differential pairs must be designed with a differential impedance of 90 Ω ± 10%.

•

To minimize crosstalk, TI recommends to keep high-speed signals away from each other. Each pair should

be separated by at least 5 times the signal trace width. Separating with ground as depicted in the layout

example also helps minimize crosstalk.

•

Route all differential pairs on the same layer adjacent to a solid ground plane.

•

Do not route differential pairs over any plane split.

•

Adding test points causes impedance discontinuity and therefore negatively impacts signal performance. If

test points are used, place them in series and symmetrically. Do not place them in a manner that causes stub

on the differential pair.

•

Avoid 90° turns in trace. Keep the use of bends in differential traces to a minimum. When bends are used, the

number of left and right bends should be as equal as possible and the angle of the bend should be

≥135°.

This guideline minimizes any length mismatch caused by the bends and therefore minimize the impact bends

have on EMI.

•

Minimize the trace lengths of the differential pair traces. Eight inches is the maximum recommended trace

length for USB 2.0 differential pair signals. Longer trace lengths require very careful routing to assure proper

signal integrity.

•

Match the etch lengths of the differential pair traces (that is DP and DM). The USB 2.0 differential pairs

should not exceed 50 mils relative trace length difference.

•

Minimize the use of vias in the differential pair paths as much as possible. If this is not practical, make sure

that the same via type and placement are used for both signals in a pair. Place any vias used as close as

possible to the TUSB4041I device.

•

To ease routing of the USB 2.0 DP and DM pair, the polarity of these pins can be swapped. If this is done,

set the appropriate Px_usb2pol register, where x = 0, 1, 2, 3, or 4.

•

Do not place power fuses across the differential pair traces.

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