TSB41AB3MPFPEP.A datasheet(30/56 Pages) TI2

30 / 56 page

TSB41AB3EP

IEEE 1394a2000 THREEPORT CABLE TRANSCEIVER/ARBITER

SGLS122C − JULY 2002 − REVISED JUNE 2008

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

APPLICATION INFORMATION

crystal selection (continued)

C10

Figure 13. Recommended Crystal and Capacitor Layout

It is strongly recommended that part of the verification process for the design be to measure the frequency of

the SYSCLK output of the PHY. This must be done with a frequency counter with an accuracy of six digits or

better. If the SYSCLK frequency is more than the crystal’s tolerance from 49.152 MHz, the load capacitance

of the crystal may be varied to improve frequency accuracy. If the frequency is too high, add more load

capacitance; if the frequency is too low, decrease load capacitance. Typically, changes are done to both load

capacitors (C9 and C10 in Figure 12) at the same time, and both must be of the same value. Additional design

details and requirements may be provided by the crystal vendor.

bus reset

In the TSB41AB3, the initiate bus reset (IBR) bit may be set to 1 in order to initiate a bus reset and initialization

sequence. The IBR bit, the root-holdoff (RHB) bit, and the gap-count register are located in PHY register 1 as

required by the 1394a-2000 Supplement (this configuration also maintains compatibility with older TI PHY

designs which were based upon the suggested register set defined in Annex J of IEEE Std 1394-1995).

Therefore, whenever the IBR bit is written, the RHB bit and gap-count are also necessarily written.

The RHB bit and gap-count may also be updated by PHY-config packets. The TSB41AB3 is 1394a-2000

compliant, and therefore both the reception and transmission of PHY-config packets cause the RHB and

gap-count to be loaded, unlike older IEEE Std 1394-1995 compliant PHYs which decode only received

PHY-config packets.

The gap-count is set to the maximum value of 63 after two consecutive bus resets without an intervening write

to the gap-count, either by a write to PHY register 1 or by a PHY-config packet. This mechanism allows a

PHY-config packet to be transmitted and then a bus reset initiated so as to verify that all nodes on the bus have

updated their RHB bits and gap-count values, without having the gap-count set back to 63 by the bus reset. The

subsequent connection of a new node to the bus, which initiates a bus reset, then causes the gap-count of each

node to be set to 63. Note, however, that if a subsequent bus reset is instead initiated by a write to register 1

to set the IBR bit, all other nodes on the bus have their gap-count values set to 63, while this node’s gap-count

remains set to the value just loaded by the write to PHY register 1.

Therefore, in order to maintain consistent gap-counts throughout the bus, the following rules apply to the use

of the IBR bit, RHB bit, and gap-count in PHY register 1:

D Following the transmission of a PHY-config packet, a bus reset must be initiated in order to verify that all

nodes have correctly updated their RHB bits and gap-count values and to ensure that a subsequent new

connection to the bus causes the gap-count to be set to 63 on all nodes in the bus. If this bus reset is initiated

by setting the IBR bit to 1, the RHB bit and gap-count register must also be loaded with the correct values

consistent with the just transmitted PHY-config packet. In the TSB41AB3, the RHB bit and gap-count is

updated to their correct values upon the transmission of the PHY-config packet, and so these values may

first be read from register 1 and then rewritten.

D Other than to initiate the bus reset, which must follow the transmission of a PHY-config packet, whenever

the IBR bit is set to 1 in order to initiate a bus reset, the gap-count value must also be set to 63 to be

consistent with other nodes on the bus. The RHB bit must be maintained with its current value.

D The PHY register 1 is not written to except to set the IBR bit. The RHB bit and gap-count are not written

without also setting the IBR bit to 1.

TSB41AB3MPFPEP.A 数据表(PDF) 30 Page - Texas Instruments

TSB41AB3MPFPEP.A 数据表(HTML) 30 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56

数据表下载