TSB41AB3MPFPEP.A datasheet(49/56 Pages) TI2

49 / 56 page

TSB41AB3EP

IEEE 1394a2000 THREEPORT CABLE TRANSCEIVER/ARBITER

SGLS122C − JULY 2002 − REVISED JUNE 2008

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

interface reset and disable (continued)

The sequence of events for initialization of the PHY-LLC interface when the interface is in the nondifferentiated

mode of operation (ISO terminal is high) is as follows:1

LPS reasserted. After the interface has been in the reset or disabled state for at least the minimum

TRESTORE time, the LLC causes the interface to be initialized and restored to normal operation by

reasserting the LPS signal. (In Figure 27, the interface is shown in the disabled state with SYSCLK low

inactive. However, the interface initialization sequence described here is also executed if the interface

is merely reset but not yet disabled.)

SYSCLK activated. If the interface is disabled, the PHY reactivates its SYSCLK output when it detects

that LPS has been reasserted. If the PHY has entered a low-power state, it takes between 5.3 ms to

7.3 ms for SYSCLK to be restored; if the PHY is not in a low-power state, SYSCLK is restored within

60 ns. The SYSCLK output is a 50% duty cycle square wave with a frequency of 49.152 MHz

±100 ppm

(period of 20.345 ns). During the first seven cycles of SYSCLK, the PHY continues to drive the CTL and

D terminals low. The LLC is also required to drive its CTL and D outputs low for one of the first six cycles

of SYSCLK but to otherwise place its CTL and D outputs in a high-impedance state. The LLC continues

to drive its LREQ output low during this time.

Receive indicated. Upon the eighth SYSCLK cycle following reassertion of LPS, the PHY asserts the

receive state on the CTL lines and the data-on indication (all ones) on the D lines for one or more cycles.

Initialization complete. The PHY asserts the Idle state on the CTL lines and logic 0 on the D lines. This

indicates that the PHY-LLC interface initialization is complete and normal operation may commence.

The PHY accepts requests from the LLC via the LREQ line.

TSB41AB3MPFPEP.A 数据表(PDF) 49 Page - Texas Instruments