TSB41AB3MPFPEP.A datasheet(8/56 Pages) TI2

8 / 56 page

TSB41AB3EP

IEEE 1394a2000 THREEPORT CABLE TRANSCEIVER/ARBITER

SGLS122C − JULY 2002 − REVISED JUNE 2008

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

Terminal Functions (Continued)

TERMINAL

I/O

DESCRIPTION

NAME

TYPE

NO.

I/O

DESCRIPTION

FILTER0

FILTER1

CMOS

I/O

PLL filter terminals. These terminals are connected to an external capacitor to form a lag-lead filter

required for stable operation of the internal frequency-multiplier PLL running off of the crystal

oscillator. A 0.1-

µF ± 10% capacitor is the only external component required to complete this filter.

ISO

CMOS

Link interface isolation control input. This terminal controls the operation of output differentiation

logic on the CTL and D terminals. If an optional isolation barrier of the type described in Annex J of

IEEE Std 1394-1995 is implemented between the TSB41AB3 and LLC, the ISO terminal is tied low to

enable the differentiation logic. If no isolation barrier is implemented (direct connection), or TI bus

holder isolation is implemented, the ISO terminal is tied high through a pullup to disable the

differentiation logic. For additional information see the TI application note Serial Bus Galvanic

Isolation, literature number SLLA011.

LPS

CMOS

5 V tol

Link power status input. This terminal is used to monitor the active/power status of the link layer

controller and to control the state of the PHY-LLC interface. This terminal is connected to either the

VDD supplying the LLC through a 10-kΩ resistor, or to a pulsed output which is active when the LLC is

powered. A pulsed signal is used when an isolation barrier exists between the LLC and PHY (see

Figure 8).

The LPS input is considered inactive if it is sampled low by the PHY for more than 2.6

µs (128

SYSCLK cycles), and is considered active otherwise (i.e., asserted steady high or an oscillating

signal with a low time less than 2.6

µs). The LPS input must be high for at least 21 ns in order to be

observed as high by the PHY.

When the TSB41AB3 detects that LPS is inactive, it places the PHY-LLC interface into a low-power

reset state. In the reset state, the CTL and D outputs are held in the logic zero state and the LREQ

input is ignored; however, the SYSCLK output remains active. If the LPS input remains low for more

than 26

µs (1280 SYSCLK cycles), the PHY-LLC interface is put into a low-power disabled state in

which the SYSCLK output is also held inactive. The PHY-LLC interface is placed into the disabled

state upon hardware reset.

The LLC is considered active only if both the LPS input is active and the LCtrl register bit is set to 1,

and is considered inactive if either the LPS input is inactive or the the LCtrl register bit is cleared to 0.

LREQ

CMOS

5 V tol

LLC request input. The LLC uses this input to initiate a service request to the TSB41AB3. Bus holder

is built into this terminal.

PC0

PC1

PC2

CMOS

Power class programming inputs. On hardware reset, these inputs set the default value of the power

class indicated during self-ID. Programming is done by tying the terminals high or low. See Table 9

for encoding.

CMOS

5 V tol

Power-down input. A high on this terminal turns off all internal circuitry except the cable-active

monitor circuits, which control the CNA output. Asserting the PD input high also activates an internal

pull-down on the RESET terminal must to force a reset of the internal control logic.

PLLGND

Supply

74, 75

−

PLL circuit ground terminals. These terminals should be tied together to the low impedance circuit

board ground plane.

PLLVDD

Supply

−

PLL circuit power terminals. A combination of high-frequency decoupling capacitors near each

terminal are suggested, such as paralleled 0.1

µF and 0.001 µF. Lower frequency 10-µF filtering

capacitors are also recommended. These supply terminals are separated from DVDD and AVDD

internal to the device to provide noise isolation. They must be tied at a low-impedance point on the

circuit board.

RESET

CMOS

Logic reset input. Asserting this terminal low resets the internal logic. An internal pullup resistor to

VDD is provided so only an external delay capacitor is required for proper power-up operation (see

power-up reset in the Application Information section). The RESET terminal also incorporates an

internal pulldown which is activated when the PD input is asserted high. This input is otherwise a

standard logic input, and can also be driven by an open-drain type driver.

Bias

−

Current setting resistor terminals. These terminals are connected to an external resistance to set the

internal operating currents and cable driver output currents. A resistance of 6.34 k

Ω ±1% is required

to meet the IEEE Std 1394-1995 output voltage limits.

CMOS

Test control input. This input is used in manufacturing test of the TSB41AB3. For normal use this

terminal is tied to GND through a 1-k

Ω pulldown resistor.

TSB41AB3MPFPEP.A 数据表(PDF) 8 Page - Texas Instruments

TSB41AB3MPFPEP.A 数据表(HTML) 8 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56

数据表下载

链接网址

TSB41AB3MPFPEP.A 数据表(PDF) 8 Page - Texas Instruments

TSB41AB3MPFPEP.A 数据表(HTML) 8 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56

数据表 下载

链接网址

数据表下载