TSB41AB3MPFPEP.A datasheet(48/56 Pages) TI2

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TSB41AB3EP

IEEE 1394a2000 THREEPORT CABLE TRANSCEIVER/ARBITER

SGLS122C − JULY 2002 − REVISED JUNE 2008

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

interface reset and disable (continued)

The sequence of events for initialization of the PHY-LLC interface when the interface is in the differentiated

mode of operation (ISO terminal is low) is as follows:1

LPS reasserted. After the interface has been in the reset or disabled state for at least the minimum

TRESTORE time, the LLC causes the interface to be initialized and restored to normal operation by

reactivating the LPS signal. (In Figure 26, the interface is shown in the disabled state with SYSCLK

high-impedance inactive. However, the interface initialization sequence described here is also

executed if the interface is merely reset but not yet disabled.)

SYSCLK activated. If the interface is disabled, the PHY reactivates its SYSCLK output when it detects

that LPS has been reasserted. If the PHY has entered a low-power state, it takes from 5.3 ms to 7.3 ms

for SYSCLK to be restored; if the PHY is not in a low-power state, SYSCLK is restored within 60 ns.

The PHY commences SYSCLK activity by driving the SYSCLK output low for half a cycle. Thereafter,

the SYSCLK output is a 50% duty cycle square wave with a frequency of 49.152 MHz

±100 ppm (period

of 20.345 ns). Upon the first full cycle of SYSCLK, the PHY drives the CTL and D terminals low for one

cycle. The LLC is also required to drive its CTL, D, and LREQ outputs low during one of the first six

cycles of SYSCLK (in Figure 26, this is shown as occurring in the first SYSCLK cycle).

Receive indicated. Upon the eighth SYSCLK cycle following reassertion of LPS, the PHY asserts the

receive state on the CTL lines and the data-on indication (all ones) on the D lines for one or more cycles

(because the interface is in the differentiated mode of operation, the CTL and D lines is in the

high-impedance state after the first cycle).

Initialization complete. The PHY asserts the idle state on the CTL lines and logic 0 on the D lines. This

indicates that the PHY-LLC interface initialization is complete and normal operation may commence.

The PHY accepts requests from the LLC via the LREQ line.

SYSCLK

ISO

(high)

(a)

(c)

(b)

CTL0

D0 − D7

LREQ

LPS

(d)

TCLK_ACTIVATE

CTL1

7 Cycles

(d)

Figure 28. Interface Initialization, ISO High

TSB41AB3MPFPEP.A 数据表(PDF) 48 Page - Texas Instruments

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