HIP2103, HIP2104

3. Specifications

FN8276 Rev.2.0

Page 8 of 30

Feb 25, 2021

3.

Specifications

3.1

Absolute Maximum Ratings

3.2

Thermal Information

Parameter (Note 5)

Minimum

Maximum

Unit

Supply Voltage VDD (HIP2103 only)

-0.3

16

V

Bridge Supply Voltage VBAT (HIP2104 Only)

-0.3

60

V

High side Bias Voltage (VHB - VHS) (Note 12)

-0.3

16

V

Logic Inputs VCen, VDen (HIP2104 Only)

- 0.3

VBAT + 0.3

V

Logic Inputs LI, HI

- 0.3

VDD + 0.3

V

Output Voltage LO

- 0.3

VDD + 0.3

V

Output Voltage HO

VHS - 0.3

VHB + 0.3

V

Voltage on HS (Note 12)

-10

60

V

Voltage on HB

VHS - 0.3

66

V

Average Current in Boot Diode (Note 6)

100

mA

Maximum Boot Capacitor Value

10

µF

Average Output Current in HO and LO (Note 6)

200

mA

ESD Rating

Value

Unit

Human Body Model Class 2 (Tested per JESD22-A114E)

2

kV

Charged Device Model Class IV

1

kV

Latch-Up (Tested per JESD-78B; Class 2, Level A) all pins

100

mA

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions can adversely

impact product reliability and result in failures not covered by warranty.

Notes:

5. All voltages are referenced to

VSS unless otherwise specified.

6. When driving a power MOSFET or similar capacitive load, the average output current is the average of the rectified output current. The

peak output currents of this driver are self limiting by trans conductance or rDS(ON) and do not require any external components to minimize

the peaks. If the output is driving a non-capacitive load, such as an LED, the maximum output current must be limited by external means

to less than the specified recommended rectified average output current.

Thermal Resistance (Typical)

θJA (°C/W)

θJC (°C/W)

8 Ld DFN Package (Notes 7, 10)46

7

12 Ld TDFN Package (Notes 7, 10)44

7

8 Ld SOIC Package (Notes 8, 9)

105

55

Notes:

7. θJA is measured in free air with the component mounted on a high-effective thermal conductivity test board with direct attach features. See

TB379.

8. θJA is measured with the component mounted on a high-effective thermal conductivity test board in free air. See TB379 for details.

9. For θJC, the case temperature location is taken at the package top center.

10. For θJC, the case temperature location is the center of the exposed metal pad on the package underside.

11. The maximum value of VHS must be limited so that VHB does not exceed 60V.

12. If the duration of the negative voltage is significant with respect to the time constant to charge the boot capacitor (across HB and HS) the

voltage on the boot capacitor can charge as high as VDD - (-VHS) = (VDD +VHS) potentially violating the Voltage Rating for (VHB - VHS).

13. When VBAT < ~13V, the output of VDD sags. The 5V minimum specified for VBAT is the minimum level for which the UVLO does not

activate.