HIP2103, HIP2104

6. Application Examples

FN8276 Rev.2.0

Page 24 of 30

Feb 25, 2021

practical application using values of Cfilter = 4700pF and RHS =1Ω, the voltage impressed on the bridge FET is

less than 1V.

The emphasis of suppressing transients on the HS pin has been with negative transients. Note: A similar

transient with a positive polarity occurs when the low-side FET turns off. This is usually not a problem unless the

bridge voltage is close to the maximum rated operating voltage of 50V. Note: The maximum voltage ratings for

the HS and HB nodes also must be observed when the positive transient occurs.

The maximum rating for (VHB - VHS) must also not be overlooked. When a negative transient, Vneg, is present

on the HS pin, the voltage differential across HB and HS approaches VDD + Vneg. If the transient duration is

short compared to the charging time constant of the boot diode and boot capacitor, the voltage across HB and HS

is not significantly affected. However, another source of negative voltage on the HS pin increases the boot

capacitor voltage. While current is flowing from the source to drain of the low-side FET during the dead time, the

current flows through body diode of the FET. Depending on the size of the FET and the amplitude of the reverse

current, the voltage across the diode can be as high as -1.5V and much higher during a load fault. Because this

negative voltage has little impedance, the boot capacitor can charge to a voltage greater than VDD (for example

VDD + 1.5V). It may be necessary to either clamp the voltage as described in Figures 25 through 27 and/or keep

the dead time as short as possible.