HIP2103, HIP2104

6. Application Examples

FN8276 Rev.2.0

Page 21 of 30

Feb 25, 2021

6.

Application Examples

Figures 3, 4, and 5 are examples of how the HIP2103 and HIP2104 can be configured for various motor drive

applications with the HIP2104 supplying the 12V bias for the other HIP2103s and the VCC (3.3V) bias for the

controller. VCen and VDen are used to turn on and off the internal linear regulators of the HIP2104. Because

entire switching of the bias supplies is implemented with logic, a signal switch, instead of a power switch, can be

used to turn on and off the driver and controller. A switch debouncing delay of 1ms is provided on VDen and

VCen.

The external diode on VBATT is used to hold up the voltage on the VBAT input in the presence of severe ripple as

usually seen on Li-ion batteries.

In the case of the HIP2104, when VDen is low, the driver sections enter Sleep Mode. When VCen is low, the bias

to the controller is removed, resulting in the lowest possible idle current in both the controller and the driver

minimizing the drain on the battery when the motor drive is off. Sleep Mode can also be initiated on the HIP2104

by driving HI and LI high simultaneously. In this case, the Sleep Mode current is substantially higher (~250µA)

because the VDD and VCC outputs are still active.

For the HIP2103, Sleep Mode is initiated when HI and LI are both high simultaneously as previously described. If

VDD is provided by an accompanying HIP2104, turning off the VDD output of the HIP2104 also results with

virtually no sleep current in the HIP2103 because there is no bias. For example, in the BLDC configuration, the

sleep mode current is ~5µA (in the HIP2104) and no current in both of the HIP2103s.

6.1

Transients on the HS Node

An important operating condition that is frequently overlooked is the transient on the HS pin that occurs when the

bridge FETs turn on or off. The Absolute Maximum negative transient (see page 8) allowed on the HS pin is -10V

without any time restrictions on the duration of the transient. In most well designed PCBs, all that is required is

that the transient is less negative than -10V.

The negative transient on the HS pin is the result of the parasitic inductance of the low-side drain-source

conductor path on the PCB. Even the parasitic inductance of the low-side FET body contributes to this transient.

When the high-side bridge FET turns off (see Figure 24 on page 22), as a consequence of the inductive

characteristics of a motor load, the current that was flowing in the high-side FET (blue) must rapidly commutate

through the low-side FET (red). The amplitude of the negative transient impressed on the HS node is (L x di/dt),

where L is the total parasitic inductance of the low-side FET drain-source path and di/dt is the rate at which the

high-side FET is turned off. With the increasing current levels of new generation motor drives, appropriately

clamping of this transient becomes more significant for the proper operation of bridge drivers. Fortunately, the

HIP2103 and HIP2104 can withstand greater amplitudes of negative transients than what is available in many

other bridge drivers. The maximum negative voltage on the HS pin is rated for -10V with no time during limit.

Another component of negative voltage is from the body diode of the low-side FET during the dead time. When

current is flowing from source to drain, the conduction voltage is approximately 1V to 1.5V negative impressed on

the HS pin (possibly greater during fault load conditions). Because the HIP2103 and HIP2104 are rated for -10V

without any time constraints, this negative voltage component is of no consequence.