HIP2103, HIP2104

5. Functional Description

FN8276 Rev.2.0

Page 19 of 30

Feb 25, 2021

5.2

Input Signals

All input logic to the HIP2103 and HIP2104 is compatible with 3.3V or 5V logic levels. The HI and LI inputs are

tolerant to voltages up to the VDD supply. The VDen and VCen (the HIP2104 LDO’s VDD and VCC enable

signals) inputs are tolerant to voltages up to VBAT.

A fail-safe mechanism is included to improve system reliability and to minimize the possibility of catastrophic

bridge failures due to controller malfunction. Internal logic prevents both outputs from turning on simultaneously

when HI and LI are both high simultaneously. Dead time is still required on the rising edge of the HI (or LI) input

when the LI (or HI) input transitions low.

5.3

Sleep Mode

The HIP2103 and HIP2104 feature a Sleep Mode operation where the drivers enter a low power state when

inactive. The HIP2103 and HIP2104’s low Sleep Mode current (quiescent current consumed by VDD bias) is

invoked by setting both the LI and HI inputs of each driver high simultaneously or if the VDD voltage enters into

UVLO. See Figures 6 and 7 for details on entering and exiting Sleep Mode. Sleep Mode only disables the half-

bridge driver outputs. The HIP2104 Sleep Mode does not control the operation of the VCC and VDD LDO. They

are controlled only by the VCen and VDen inputs. Upon VDD power up (and clearing UVLO status), the HIP2103

and HIP2104 remains in Sleep Mode until it is exited by setting LI = 1 for time period tSIpR.

5.4

Selecting the Boot Capacitor Value

The boot capacitor value is chosen not only to supply the internal bias current of the high-side driver but more

significantly, to provide the gate charge of the driven FET without causing the boot voltage to sag excessively. In

practice, the boot capacitor should have a total charge that is about 20 times the gate charge of the driven power

FET for approximately a 5% drop in voltage after charge has been transferred from the boot capacitor to the gate

capacitance.

The following parameters are required to calculate the value of the boot capacitor for a specific amount of voltage

droop when using the HIP2103 and HIP2104. In the following example, some values used are specific to the

HIP2103 and HIP2104 and others are arbitrary. The values should be changed to comply with the actual

application.

The following equations calculate the total charge required for the Period:

Qc = Qg40_12V + Period x (IHB + VHO/RGS + Igate_leak)

Cboot = Qc/(Ripple * VDD)

Cboot = 0.324µF

If the gate-to-source resistor is removed (RGS is usually not needed or recommended):

Cboot = 0.124µF

VDD = 12V

This is the nominal value of VDD for the HIP2104

VHB = VDD = VHO

High-side driver bias voltage referenced to VHS

Period = 100µs

This is the longest expected switching period

IHB = IHBS20K + IHB20K = 295µA

High-side driver bias current at 20kHz

RGS = 10kΩ

Gate-source resistor

Ripple = 5%

Desired ripple voltage on the boot capacitor

Igate_leak = 100nA

Gate leakage current (from vendor datasheet)

Qg40_12V = 45nC

From Figure 23 on page 20