LP8550TLX-ASLASHNOPB datasheet(13/49 Pages) TI2

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5MHz internal

oscillator

PLL[12:0]

PWM generation

PWM_FREQ[4:0]

or External

set resistor RFSET

VBOOST

LED Drivers 1-6

Divider

1/N

5 MHz...40 MHz

PSPWM 0/1

Boost

Filter

VCO

Counter

1/N

PLL

VSYNC

60 Hz

EN_VSYNC

Phase

Detector

State machine,

PWM input, internal

timings, Slope etc.

BOOST_FREQ

N = 4, 8, 16, 32

PWM_RESOLUTION[1:0]

LP8550

www.ti.com

SNVS657E – SEPTEMBER 2010 – REVISED SEPTEMBER 2014

Feature Description (continued)

Figure 12. Principle Of The Clock Generation

8.3.2 Brightness Control Methods

LP8550 controls the brightness of the backlight with PWM. PWM control is received either from PWM input pin or

from I2C register bits. The PWM source selection is done with <BRT_MODE[1:0]> bits as follows:

BRT_MODE[1]

BRT_MODE[0]

PWM SOURCE

PWM input pin duty cycle control. Default.

PWM input pin duty cycle control.

Brightness register

PWM direct control (PWM in = PWM out)

8.3.2.1 PWM Input Duty Cycle

With PWM input pin duty cycle control the output PWM is controlled by PWM input duty cycle. PWM detector

block measures the duty cycle in the PWM pin and uses this 13-bit value to generate the output PWM. Output

PWM can have different frequency than input in this mode and also phase shift PWM mode can be used. Slope

and dither are effective in this mode. PWM input resolution is defined by the input PWM clock frequency.

8.3.2.2 Brightness Register Control

With brightness register control the output PWM is controlled with 8-bit resolution <BRT7:0> register bits. Phase

shift scheme can be used with this and the output PWM frequency can be freely selected. Slope and dither are

effective in this mode.

8.3.2.3 PWM Direct Control

With PWM direct control the output PWM directly follows the input PWM. Due to the internal logic structure the

input is anyway clocked with the 5 MHz clock or the PLL clock. PSPWM mode is not possible in this mode. Slope

and dither are not effective in this mode.

8.3.2.4 PWM Calculation Data Flow

Figure 13 shows a flow chart of the PWM calculation data flow. In PWM direct control mode most of the blocks

are bypassed and this flow chart does not apply.

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