LP8550TLX-ASLASHNOPB datasheet(25/49 Pages) TI2

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'0'

Slave Address

(7 bits)

Control Register Add.

(8 bits)

Data- Data

(8 bits)

R/W

Data transfered, byte +

Ack/NAck

Slave Address

(7 bits)

'1' A

R/W

Direction of the transfer

will change at this point

From Master to Slave

From Slave to Master

A - ACKNOWLEDGE (SDA Low)

S - START CONDITION

P - STOP CONDITION

Sr - REPEATED START CONDITION

NA - ACKNOWLEDGE (SDA High)

'0'

Slave Address

(7 bits)

Control Register Add.

(8 bits)

R/W

From Master to Slave

From Slave to Master

A - ACKNOWLEDGE (SDA Low)

S - START CONDITION

P - STOP CONDITION

Data transfered,

byte + Ack

LP8550

www.ti.com

SNVS657E – SEPTEMBER 2010 – REVISED SEPTEMBER 2014

<>Data from master [ ] Data from slave

Figure 24. Register Write

Figure 25. Register Read

8.5.2 EEPROM

EEPROM memory stores various parameters for chip control. The 64-bit EEPROM memory is organized as 8 x 8

bits. The EEPROM structure consists of a register front-end and the non-volatile memory (NVM). Register data

can be read and written through the serial interface, and data is effective immediately. To read and program

NVM, separate commands need to be sent. Erase and program voltages are generated on-chip charge pump, no

other voltages than normal input voltage are required. A complete EEPROM memory map is shown in the

EEPROM Register Map.

NOTE

EEPROM NVM can be programmed or read by customer for bench validation.

Programming for production devices should be done in TI production test, where

appropriate checks are performed to confirm EEPROM validity. Writing to EEPROM

Control register of production devices (for burning or reading EEPROM) is not

recommended. If special EEPROM configuration is required, please contact the TI Sales

Office for availability.

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