LP8550TLX-ASLASHNOPB datasheet(41/49 Pages) TI2

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MCU

LP8550

VLDO

GND_LED

ISET

VDDIO

PWM

SCLK

SDA

OUT1

OUT2

OUT3

OUT4

10V ± 40V

5.5V ± 22V

FSET

15 éH

GND

210 mA ± 400 mA

COUT

CIN

2 x 10 éF

CVLDO

1 éF

VDDIO reference voltage

FAULT

Can be left floating

39 pF

VIN

16 k

91 k

VBATT

GND_S

GND_SW

RED line = keep routes short

Sensitive node, quiet ground!

100 nF

OUT5

OUT6

LP8550

www.ti.com

SNVS657E – SEPTEMBER 2010 – REVISED SEPTEMBER 2014

Layout Guidelines (continued)

frequency ripple affecting the chip behavior. Separate 100-nF bypass capacitor is used for VIN line and it is

grounded to noise-free ground.

10. Input and output capacitors need strong grounding (wide traces, vias to GND plane).

11. If two output capacitors are used they need symmetrical layout to get both capacitors working ideally.

12. Output capacitors DC-bias effect. If the output capacitance is too low, it can cause boost to become

unstable on some loads and this increases EMI. DC bias characteristics need to be obtained from the

component manufacturer; it is not taken into account on component tolerance. 50-V 1210-size X5R/X7R

capacitors are recommended.

11.2 Layout Examples

Figure 32. LP8550 Application Schematic for Layout

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