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LP3921 数据表(PDF) 35 Page - Texas Instruments |
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LP3921 数据表(HTML) 35 Page - Texas Instruments |
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35 / 44 page ![]() R/W S Slave Address (7 bits) '0' A A Control Register Add. (8 bits) From Slave to Master From Master to Slave Slave Address (7 bits) A Sr '1' R/W Data transferred, byte + Ack/NAck Register Data (8 bits) P A - ACKNOWLEDGE (SDA Low) S - START CONDITION P - STOP CONDITION NA - ACKNOWLEDGE (SDA High) Sr - REPEATED START CONDITION Direction of the transfer will change at this point NA A/ LP3921 www.ti.com SNVS580A – AUGUST 2008 – REVISED MAY 2013 Figure 15. Register Read Format Copyright © 2008–2013, Texas Instruments Incorporated Submit Documentation Feedback 35 Product Folder Links: LP3921 |
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