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LP3921 数据表(PDF) 13 Page - Texas Instruments |
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LP3921 数据表(HTML) 13 Page - Texas Instruments |
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13 / 44 page ![]() LP3921 www.ti.com SNVS580A – AUGUST 2008 – REVISED MAY 2013 Audio Electrical Characteristics Unless otherwise noted, VDD= 3.6V Typical values and limits appearing in normal type apply for TJ = 25°C. Limits appearing in boldface type apply over the entire junction temperature range for operation, TA= TJ = −25°C to +85°C. (1) Limit Symbol Paramater Conditions Typical Units Min Max PO Output Power THD = 1% (max); 0.375 W f = 1 kHz, RL = 8Ω THD + N Total Harmonic Distortion PO = 0.25 Wrms; 0.02 % + Noise f = 1 kHz Vripple = 200 mVPP Power Supply Rejection PSRR f = 217 Hz 85 dB Ratio f = 1 kHz 85 73 CMRR Common-Mode Rejection f = 217 Hz, 50 dB Ratio VCM = 200 mVPP VOS Output Offset VacINput = 0V 4 mV (1) All limits are verified. All electrical characteristics having room-temperature limits are tested during production with TJ = 25°C. All hot and cold limits are specified by correlating the electrical characteristics to process and temperature variations and applying statistical process control. Serial Interface Unless otherwise noted, VIN ( = VIN1 = VIN2 = BATT=VDD) = 3.6V, GND = 0V, CVIN1-2=10 µF, CLDOX=1 µF, and VLDO2 (DIGI) ≥ 1.8V. Typical values and limits appearing in normal type apply for TJ = 25°C. Limits appearing in boldface type apply over the entire junction temperature range for operation, TA= TJ = −40°C to +125°C. (1) (2) Limit Symbol Parameter Condition Typ Units Min Max fCLK Clock Frequency 400 kHz tBF Bus-Free Time between 1.3 µs START and STOP tHOLD Hold Time Repeated START 0.6 µs Condition tCLK-LP CLK Low Period 1.3 µs tCLK-HP CLK High Period 0.6 µs tSU Set-Up Time Repeated 0.6 µs START Condition tDATA-HOLD Data Hold Time 50 ns tDATA-SU Data Set-Up Time 100 ns tSU Set-Up Time for STOP 0.6 µs Condition tTRANS Maximum Pulse Width of 50 ns Spikes that Must be Suppressed by the Input Filter of both DATA & CLK Signals (1) All limits are verified. All electrical characteristics having room-temperature limits are tested during production with TJ = 25°C. All hot and cold limits are specified by correlating the electrical characteristics to process and temperature variations and applying statistical process control. (2) Specified by design. Copyright © 2008–2013, Texas Instruments Incorporated Submit Documentation Feedback 13 Product Folder Links: LP3921 |
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